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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 11:36:03 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 11:36:03 +0000
commit6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23 (patch)
tree1b06518d371222763417675b38161d261bd42f93 /src/mainboard/intel
parent86a571797d9ede9d79edcfdce38f50a80b9a49f9 (diff)
downloadcoreboot-6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23.tar.xz
Use DIMM0 et al in lots more places instead of hardocding values.
The (0xa << 3) expression equals 0x50, i.e. DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c5
-rw-r--r--src/mainboard/intel/jarrell/romstage.c9
-rw-r--r--src/mainboard/intel/mtarvon/romstage.c5
-rw-r--r--src/mainboard/intel/truxton/romstage.c2
-rw-r--r--src/mainboard/intel/xe7501devkit/romstage.c8
5 files changed, 14 insertions, 15 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 07ba0a0bdf..d70798c8a2 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -78,6 +78,7 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "lib/generic_sdram.c"
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
+#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
@@ -136,8 +137,8 @@ void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
- .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
- .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+ .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+ .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
}
};
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 530c22ae24..22f5937e02 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -19,6 +19,7 @@
#include "superio/nsc/pc87427/pc87427_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
+#include <spd.h>
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@@ -41,10 +42,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
- /*
- *
- *
- */
static const struct mem_controller mch[] = {
{
.node_id = 0,
@@ -54,8 +51,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
- .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
- .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
+ .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
+ .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
};
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index f36e4a4e68..5d34058a84 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -36,6 +36,7 @@
#include "superio/intel/i3100/i3100_early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
+#include <spd.h>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@@ -64,8 +65,8 @@ void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
- .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
- .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+ .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
+ .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
}
};
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 105b82115c..32cca1cfbf 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -61,7 +61,7 @@ static void main(unsigned long bist)
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x00, 0),
- .channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
+ .channel0 = { DIMM2, DIMM3 },
}
};
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index c04d63790c..4505cf2c91 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -16,9 +16,9 @@
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+#include <spd.h>
-#define SUPERIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
static void hard_reset(void)
{
@@ -41,8 +41,8 @@ static void main(unsigned long bist)
{
.d0 = PCI_DEV(0, 0, 0),
.d0f1 = PCI_DEV(0, 0, 1),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
- .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+ .channel0 = { DIMM0, DIMM1, DIMM2, 0 },
+ .channel1 = { DIMM4, DIMM5, DIMM6, 0 },
},
};