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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:56:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 18:06:27 +0000 |
| commit | 7843bd560e65b0a83e99b42bdd58dd6363656c56 (patch) | |
| tree | 0d411ba99ae94da46d3fccaf09f1208fc812bb6f /src/mainboard/intel | |
| parent | c583920a748fb8bd7999142433ad08641b06283d (diff) | |
| download | coreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.tar.xz | |
nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/dg41wv/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/dg41wv/early_init.c (renamed from src/mainboard/intel/dg41wv/romstage.c) | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/dg43gt/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/dg43gt/early_init.c (renamed from src/mainboard/intel/dg43gt/romstage.c) | 3 |
4 files changed, 10 insertions, 2 deletions
diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/intel/dg41wv/Makefile.inc +++ b/src/mainboard/intel/dg41wv/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/early_init.c index ff018af5f6..3cb40955d0 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pnp_ops.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 6b3d94a037..f89d1302e3 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -14,4 +14,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/early_init.c index 71fd87ad74..8457707ba1 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <southbridge/intel/i82801jx/i82801jx.h> #include <northbridge/intel/x4x/x4x.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -21,7 +22,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; |