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authorLee Leahy <leroy.p.leahy@intel.com>2016-01-26 10:06:42 -0800
committerMartin Roth <martinroth@google.com>2016-02-04 19:20:06 +0100
commit93dd5f78ffc7d9f9311866c38afc78062c6a52ef (patch)
tree05b81477ef8ef3e4009861fd390af50b5ee635da /src/mainboard/intel
parent4af905ac95685500e71fb32cf5cec430d1a75447 (diff)
downloadcoreboot-93dd5f78ffc7d9f9311866c38afc78062c6a52ef.tar.xz
mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/galileo/Kconfig36
-rw-r--r--src/mainboard/intel/galileo/Kconfig.name17
-rw-r--r--src/mainboard/intel/galileo/Makefile.inc16
-rw-r--r--src/mainboard/intel/galileo/devicetree.cb24
-rw-r--r--src/mainboard/intel/galileo/romstage.c24
5 files changed, 117 insertions, 0 deletions
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
new file mode 100644
index 0000000000..cae136f4f2
--- /dev/null
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_INTEL_GALILEO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select PLATFORM_USES_FSP1_1
+ select SOC_INTEL_QUARK
+
+config MAINBOARD_DIR
+ string
+ default intel/galileo
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Galileo"
+
+config MAINBOARD_VENDOR
+ string
+ default "Intel"
+
+endif # BOARD_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name
new file mode 100644
index 0000000000..124aa7a737
--- /dev/null
+++ b/src/mainboard/intel/galileo/Kconfig.name
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_INTEL_GALILEO
+ bool "Galileo"
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
new file mode 100644
index 0000000000..3ffba1c963
--- /dev/null
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
new file mode 100644
index 0000000000..ab4f246fda
--- /dev/null
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/quark
+
+ device domain 0 on
+ # EDS Table 3
+ device pci 00.0 on end # 8086 0958 - Host Bridge
+ device pci 1f.0 on end # 8086 095e - Legacy Bridge
+ end
+end
diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c
new file mode 100644
index 0000000000..dfae772580
--- /dev/null
+++ b/src/mainboard/intel/galileo/romstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/romstage.h>
+
+/* All FSP specific code goes in this block */
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ /* Call back into chipset code with platform values updated. */
+ romstage_common(rp);
+}