Move generation of mptable entries for ISA to generic code.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 7 insertions, 136 deletions

diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 62850ebf1c..bff9849020 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -69,20 +69,7 @@ static void *smp_write_config_table(void *v)
 
 	/* Legacy Interrupts */
 
-	/* I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
+	mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
 
 	/* Builtin devices on Bus 0 */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 74147cf888..5ee1d1f44b 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -179,39 +179,7 @@ static void *smp_write_config_table(void *v)
                 }
 	}
 	*/
-	/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	/* IRQ0 8254 Counter 0, MNT0 */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  0);
-	/* IRQ1 Keyboard */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  1, IO_APIC0,  1);
-	/* IRQ2 8259 cascade only */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  2);
-	/* IRQ3 COM2, Option for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  3, IO_APIC0,  3);
-	/* IRQ4 COM1, Option for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  4, IO_APIC0,  4);
-	/* IRQ5 Option for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  5, IO_APIC0,  5);
-	/* IRQ6 Option for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  6, IO_APIC0,  6);
-	/* IRQ7 OPtion for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  7, IO_APIC0,  7);
-	/* IRQ8# RTC, MNT1 */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_EDGE   |MP_IRQ_POLARITY_HIGH,    bus_isa,  8, IO_APIC0,  8);
-	/* IRQ9 Option for PIRQx, SCI, TCO */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  9, IO_APIC0,  9);
-	/* IRQ10 Option for PIRQx, SCI, TCO */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
-	/* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
-	/* IRQ12 Mouse, Option for PIRQx */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
-	/* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
-	/* IRQ14 PIRQx Sata primary (legacy mode) */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
-	/* IRQ15 PIRQx Sata secondary (legacy mode) */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+	mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
 
 	/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index 1386c16183..863ddf8a0e 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -166,31 +166,8 @@ static void *smp_write_config_table(void *v)
 		}
 	}
 
-	/* ISA backward compatibility interrupts  */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x08, 0x00);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x01, 0x08, 0x01);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x08, 0x02);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x03, 0x08, 0x03);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x04, 0x08, 0x04);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x06, 0x08, 0x06);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x08, 0x08, 0x08);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x09, 0x08, 0x09);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0c, 0x08, 0x0c);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0d, 0x08, 0x0d);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0e, 0x08, 0x0e);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0f, 0x08, 0x0f);
+	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
+
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 		bus_isa, 0x0a, 0x08, 0x10);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index da94a99faa..8d600ddd30 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -64,31 +64,7 @@ static void *smp_write_config_table(void *v)
 	/* IOAPIC handling */
 	smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
 
-	/* ISA backward compatibility interrupts  */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x01, 0x00);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x01, 0x01, 0x01);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x01, 0x02);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x03, 0x01, 0x03);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x04, 0x01, 0x04);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x06, 0x01, 0x06);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x08, 0x01, 0x08);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x09, 0x01, 0x09);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0c, 0x01, 0x0c);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0d, 0x01, 0x0d);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0e, 0x01, 0x0e);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0f, 0x01, 0x0f);
+	mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
 
 	/* Standard local interrupt assignments */
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 2b63d2abd8..c80d5d3be3 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -97,31 +97,7 @@ static void *smp_write_config_table(void *v)
 	/* IOAPIC handling */
 	smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
 
-	/* ISA backward compatibility interrupts */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x8, 0x00);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x01, 0x8, 0x01);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, 0x8, 0x02);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x03, 0x8, 0x03);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x04, 0x8, 0x04);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x06, 0x8, 0x06);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-		bus_isa, 0x08, 0x8, 0x08);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x09, 0x8, 0x09);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0c, 0x8, 0x0c);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0d, 0x8, 0x0d);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0e, 0x8, 0x0e);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x0f, 0x8, 0x0f);
+	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
 
 	/* Standard local interrupt assignments */
 	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 2f48e83285..ed81884122 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -126,20 +126,7 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 
 	// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
 
-	// Super I/O (ISA interrupts)
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 0,					IOAPIC_ICH3,			 0);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 1,					IOAPIC_ICH3,			 1);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 0,					IOAPIC_ICH3,			 2);
-
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 3,					IOAPIC_ICH3,			 3);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 4,					IOAPIC_ICH3,			 4);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 6,					IOAPIC_ICH3,			 6);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 8,					IOAPIC_ICH3,			 8);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		 9,					IOAPIC_ICH3,			 9);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		12,					IOAPIC_ICH3,			12);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		13,					IOAPIC_ICH3,			13);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		14,					IOAPIC_ICH3,			14);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH,	SUPERIO_BUS,		15,					IOAPIC_ICH3,			15);
+	mptable_add_isa_interrupts(mc, SUPERIO_BUS, IOAPIC_ICH3, 0);
 }
 
 static void *smp_write_config_table(void* v)