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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 18:42:40 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-21 06:40:11 +0000
commiteb5147027e974ba365aa4706935c7c9582cf7619 (patch)
treed6ddb25625b91a6db86b7680ca3c92755044a31e /src/mainboard/intel
parentc2c634a089fa990418c363e2ff2e5ff70bdd3580 (diff)
downloadcoreboot-eb5147027e974ba365aa4706935c7c9582cf7619.tar.xz
mb/*/*: Drop FSP_BAYTRAIL support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/bayleybay_fsp/Kconfig67
-rw-r--r--src/mainboard/intel/bayleybay_fsp/Kconfig.name5
-rw-r--r--src/mainboard/intel/bayleybay_fsp/Makefile.inc17
-rw-r--r--src/mainboard/intel/bayleybay_fsp/acpi/ec.asl0
-rw-r--r--src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl20
-rw-r--r--src/mainboard/intel/bayleybay_fsp/acpi/superio.asl0
-rw-r--r--src/mainboard/intel/bayleybay_fsp/acpi_tables.c58
-rw-r--r--src/mainboard/intel/bayleybay_fsp/board_info.txt5
-rw-r--r--src/mainboard/intel/bayleybay_fsp/chromeos.fmd37
-rw-r--r--src/mainboard/intel/bayleybay_fsp/cmos.layout97
-rw-r--r--src/mainboard/intel/bayleybay_fsp/devicetree.cb76
-rw-r--r--src/mainboard/intel/bayleybay_fsp/dsdt.asl54
-rw-r--r--src/mainboard/intel/bayleybay_fsp/fadt.c29
-rw-r--r--src/mainboard/intel/bayleybay_fsp/gpio.c220
-rw-r--r--src/mainboard/intel/bayleybay_fsp/irqroute.c18
-rw-r--r--src/mainboard/intel/bayleybay_fsp/irqroute.h82
-rw-r--r--src/mainboard/intel/bayleybay_fsp/mainboard.c35
-rw-r--r--src/mainboard/intel/bayleybay_fsp/romstage.c168
-rw-r--r--src/mainboard/intel/bayleybay_fsp/thermal.h29
-rw-r--r--src/mainboard/intel/minnowmax/Kconfig64
-rw-r--r--src/mainboard/intel/minnowmax/Kconfig.name2
-rw-r--r--src/mainboard/intel/minnowmax/Makefile.inc17
-rw-r--r--src/mainboard/intel/minnowmax/acpi/ec.asl0
-rw-r--r--src/mainboard/intel/minnowmax/acpi/mainboard.asl20
-rw-r--r--src/mainboard/intel/minnowmax/acpi/superio.asl0
-rw-r--r--src/mainboard/intel/minnowmax/acpi_tables.c48
-rw-r--r--src/mainboard/intel/minnowmax/board_info.txt4
-rw-r--r--src/mainboard/intel/minnowmax/cmos.layout108
-rw-r--r--src/mainboard/intel/minnowmax/devicetree.cb93
-rw-r--r--src/mainboard/intel/minnowmax/dsdt.asl54
-rw-r--r--src/mainboard/intel/minnowmax/fadt.c29
-rw-r--r--src/mainboard/intel/minnowmax/gpio.c232
-rw-r--r--src/mainboard/intel/minnowmax/irqroute.c18
-rw-r--r--src/mainboard/intel/minnowmax/irqroute.h83
-rw-r--r--src/mainboard/intel/minnowmax/mainboard.c41
-rw-r--r--src/mainboard/intel/minnowmax/romstage.c140
36 files changed, 0 insertions, 1970 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
deleted file mode 100644
index 4a08fb1f78..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select SOC_INTEL_FSP_BAYTRAIL
- select BOARD_ROMSIZE_KB_2048
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
- select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-
-config MAINBOARD_DIR
- string
- default "intel/bayleybay_fsp"
-
-config MAINBOARD_PART_NUMBER
- string
- default "Bakersport CRB (FSP)" if BOARD_INTEL_BAKERSPORT_FSP
- default "Bayley Bay CRB (FSP)"
-
-config MAX_CPUS
- int
- default 16
-
-config FSP_FILE
- string
- default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
- default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
-
-config CBFS_SIZE
- hex
- default 0x00200000
-
-config ENABLE_FSP_FAST_BOOT
- bool
- depends on HAVE_FSP_BIN
- default y
-
-config VIRTUAL_ROM_SIZE
- hex
- depends on ENABLE_FSP_FAST_BOOT
- default 0x800000
-
-config FSP_PACKAGE_DEFAULT
- bool "Configure defaults for the Intel FSP package"
- default n
-
-config VGA_BIOS
- bool
- default y if FSP_PACKAGE_DEFAULT
-
-endif # BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig.name b/src/mainboard/intel/bayleybay_fsp/Kconfig.name
deleted file mode 100644
index 524c616ac2..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig.name
+++ /dev/null
@@ -1,5 +0,0 @@
-config BOARD_INTEL_BAKERSPORT_FSP
- bool "Bakersport FSP-based CRB"
-
-config BOARD_INTEL_BAYLEYBAY_FSP
- bool "Bayley Bay FSP-based CRB"
diff --git a/src/mainboard/intel/bayleybay_fsp/Makefile.inc b/src/mainboard/intel/bayleybay_fsp/Makefile.inc
deleted file mode 100644
index 3074df2138..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += gpio.c
-ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl b/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl b/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl
deleted file mode 100644
index b032ee189d..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
- Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/superio.asl b/src/mainboard/intel/bayleybay_fsp/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c
deleted file mode 100644
index d81798c6b0..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include <soc/iomap.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- acpi_init_gnvs(gnvs);
-
- /* Enable USB ports in S3 */
- gnvs->s3u0 = 1;
- gnvs->s3u1 = 1;
-
- /* Disable USB ports in S5 */
- gnvs->s5u0 = 0;
- gnvs->s5u1 = 0;
-
- /* TPM Present */
- gnvs->tpmp = 0;
-
- /* Enable DPTF */
- gnvs->dpte = 0;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- current = acpi_madt_irq_overrides(current);
-
- return current;
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/board_info.txt b/src/mainboard/intel/bayleybay_fsp/board_info.txt
deleted file mode 100644
index 69232e6d6e..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: Bayley Bay
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Release year: 2014
diff --git a/src/mainboard/intel/bayleybay_fsp/chromeos.fmd b/src/mainboard/intel/bayleybay_fsp/chromeos.fmd
deleted file mode 100644
index 7be08dc27b..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/chromeos.fmd
+++ /dev/null
@@ -1,37 +0,0 @@
-FLASH@0xff800000 0x800000 {
- SI_ALL@0x0 0x300000 {
- SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x2ff000
- }
- SI_BIOS@0x300000 0x500000 {
- RW_SECTION_A@0x0 0xf0000 {
- VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0xc0000
- RW_FWID_A@0xeffc0 0x40
- }
- RW_SECTION_B@0xf0000 0xf0000 {
- VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0xc0000
- RW_FWID_B@0xeffc0 0x40
- }
- RW_MRC_CACHE@0x1e0000 0x10000
- RW_ELOG(PRESERVE)@0x1f0000 0x4000
- RW_SHARED@0x1f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
- }
- RW_VPD(PRESERVE)@0x1f8000 0x2000
- RW_UNUSED@0x1fa000 0x106000
- WP_RO@0x300000 0x200000 {
- RO_VPD(PRESERVE)@0x0 0x4000
- RO_UNUSED@0x4000 0xc000
- RO_SECTION@0x10000 0x1f0000 {
- FMAP@0x0 0x800
- RO_FRID@0x800 0x40
- RO_FRID_PAD@0x840 0x7c0
- GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x100000
- }
- }
- }
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/cmos.layout b/src/mainboard/intel/bayleybay_fsp/cmos.layout
deleted file mode 100644
index 61b99327e6..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/cmos.layout
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392 3 r 0 unused
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
deleted file mode 100644
index 28caa54104..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ /dev/null
@@ -1,76 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/fsp_baytrail
-
- #### ACPI Register Settings ####
- register "fadt_pm_profile" = "PM_MOBILE"
- register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
-
- #### FSP register settings ####
- register "PcdSataMode" = "SATA_MODE_AHCI"
- register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
- register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
- register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
- register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
- register "PcdGttSize" = "GTT_SIZE_DEFAULT"
- register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
- register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
- register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- device domain 0 on
- device pci 00.0 on end # 8086 0F00 - SoC router
- device pci 02.0 on end # 8086 0F31 - GFX
- device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
-
- device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
- device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
- device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
- device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
- device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
- device pci 15.0 off end # 8086 0F28 - LP Engine Audio
- device pci 16.0 off end # 8086 0F37 - OTG controller
- device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
- device pci 18.0 on end # 8086 0F40 - SIO - DMA
- device pci 18.1 on end # 8086 0F41 - I2C Port 1
- device pci 18.2 on end # 8086 0F42 - I2C Port 2
- device pci 18.3 on end # 8086 0F43 - I2C Port 3
- device pci 18.4 on end # 8086 0F44 - I2C Port 4
- device pci 18.5 on end # 8086 0F45 - I2C Port 5
- device pci 18.6 on end # 8086 0F46 - I2C Port 6
- device pci 18.7 on end # 8086 0F47 - I2C Port 7
- device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
- device pci 1b.0 on end # 8086 0F04 - HD Audio
- device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot)
- device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
- device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
- device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
- device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
- device pci 1e.0 on end # 8086 0F06 - SIO - DMA
- device pci 1e.1 on end # 8086 0F08 - PWM 1
- device pci 1e.2 on end # 8086 0F09 - PWM 2
- device pci 1e.3 on end # 8086 0F0A - HSUART 1
- device pci 1e.4 on end # 8086 0F0C - HSUART 2
- device pci 1e.5 on end # 8086 0F0E - SPI
- device pci 1f.0 on end # 8086 0F1C - LPC bridge
- device pci 1f.3 on end # 8086 0F12 - SMBus 0
- end
-end
diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl
deleted file mode 100644
index bea6af7973..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define INCLUDE_LPE 1
-#define INCLUDE_SCC 1
-#define INCLUDE_EHCI 1
-#define INCLUDE_XHCI 1
-#define INCLUDE_LPSS 1
-
-
-#include <arch/acpi.h>
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0 and up
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/fsp_baytrail/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
-
- #include <cpu/intel/common/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
- }
- }
-
- /* Chipset specific sleep states */
- #include <southbridge/intel/common/acpi/sleepstates.asl>
-
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/fadt.c b/src/mainboard/intel/bayleybay_fsp/fadt.c
deleted file mode 100644
index 8fee54b63e..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/fadt.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- acpi_fill_in_fadt(fadt,facs,dsdt);
-
- /* Platform specific customizations go here */
-
- header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/gpio.c b/src/mainboard/intel/bayleybay_fsp/gpio.c
deleted file mode 100644
index 27b22c5e17..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/gpio.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <soc/gpio.h>
-#include "irqroute.h"
-
-/* NCORE GPIOs */
-static const struct soc_gpio_map gpncore_gpio_map[] = {
- GPIO_FUNC2, /* GPIO 0 */
- GPIO_FUNC2, /* GPIO 1 */
- GPIO_FUNC2, /* GPIO 2 */
- GPIO_FUNC2, /* GPIO 3 */
- GPIO_FUNC2, /* GPIO 4 */
- GPIO_FUNC2, /* GPIO 5 */
- GPIO_FUNC2, /* GPIO 6 */
- GPIO_FUNC2, /* GPIO 7 */
- GPIO_FUNC2, /* GPIO 8 */
- GPIO_FUNC2, /* GPIO 9 */
- GPIO_FUNC2, /* GPIO 10 */
- GPIO_FUNC2, /* GPIO 11 */
- GPIO_FUNC2, /* GPIO 12 */
- GPIO_FUNC2, /* GPIO 13 */
- GPIO_FUNC2, /* GPIO 14 */
- GPIO_FUNC2, /* GPIO 15 */
- GPIO_FUNC2, /* GPIO 16 */
- GPIO_FUNC2, /* GPIO 17 */
- GPIO_FUNC2, /* GPIO 18 */
- GPIO_FUNC2, /* GPIO 19 */
- GPIO_FUNC2, /* GPIO 20 */
- GPIO_FUNC2, /* GPIO 21 */
- GPIO_FUNC2, /* GPIO 22 */
- GPIO_FUNC2, /* GPIO 23 */
- GPIO_FUNC2, /* GPIO 24 */
- GPIO_FUNC2, /* GPIO 25 */
- GPIO_FUNC2, /* GPIO 26 */
- GPIO_END
-};
-
-/* SCORE GPIOs (GPIO_S0_SC_XX)*/
-static const struct soc_gpio_map gpscore_gpio_map[] = {
- GPIO_FUNC1, /* GPIO_S0_SC[000] SATA_GP[0] - - - */
- GPIO_FUNC2, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] - - */
- GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# - - - */
- GPIO_NC, /* GPIO_S0_SC[007] RESERVED SD3_WP - - */
- GPIO_FUNC2, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# - - */
- GPIO_FUNC2, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC - - */
- GPIO_FUNC2, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK - - */
- GPIO_FUNC2, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO - - */
- GPIO_FUNC2, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] - - */
- GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED - - */
- GPIO_NC, /* GPIO_S0_SC[016] MMC1_CLK - MMC1_45_CLK - */
- GPIO_NC, /* GPIO_S0_SC[017] MMC1_D[0] - MMC1_45_D[0] - */
- GPIO_NC, /* GPIO_S0_SC[018] MMC1_D[1] - MMC1_45_D[1] - */
- GPIO_NC, /* GPIO_S0_SC[019] MMC1_D[2] - MMC1_45_D[2] - */
- GPIO_NC, /* GPIO_S0_SC[020] MMC1_D[3] - MMC1_45_D[3] - */
- GPIO_NC, /* GPIO_S0_SC[021] MMC1_D[4] - MMC1_45_D[4] - */
- GPIO_NC, /* GPIO_S0_SC[022] MMC1_D[5] - MMC1_45_D[5] - */
- GPIO_NC, /* GPIO_S0_SC[023] MMC1_D[6] - MMC1_45_D[6] - */
- GPIO_NC, /* GPIO_S0_SC[024] MMC1_D[7] - MMC1_45_D[7] - */
- GPIO_NC, /* GPIO_S0_SC[025] MMC1_CMD - MMC1_45_CMD - */
- GPIO_NC, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# - */
- GPIO_FUNC1, /* GPIO_S0_SC[027] SD2_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[028] SD2_D[0] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[029] SD2_D[1] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[030] SD2_D[2] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[031] SD2_D[3]_CD# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[032] SD2_CMD - - - */
- GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK - - - */
- GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] - - - */
- GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] - - - */
- GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] - - - */
- GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] - - - */
- GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# - - - */
- GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD - - - */
- GPIO_NC, /* GPIO_S0_SC[040] SD3_1P8EN - - - */
- GPIO_NC, /* GPIO_S0_SC[041] SD3_PWREN# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[055] RESERVED - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[056] RESERVED - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[058] RESERVED - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[059] RESERVED - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[060] RESERVED - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED - */
- GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED - - */
- GPIO_FUNC1, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[066] SIO_SPI_CS# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[067] SIO_SPI_MISO - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[068] SIO_SPI_MOSI - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[069] SIO_SPI_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED - - */
- GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED - - */
- GPIO_FUNC1, /* GPIO_S0_SC[072] SIO_UART1_RTS# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[073] SIO_UART1_CTS# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[074] SIO_UART2_RXD - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[075] SIO_UART2_TXD - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[076] SIO_UART2_RTS# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[077] SIO_UART2_CTS# - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[080] SIO_I2C1_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED - - */
- GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[084] SIO_I2C3_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[085] SIO_I2C3_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[086] SIO_I2C4_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[087] SIO_I2C4_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[088] SIO_I2C5_DATA - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[089] SIO_I2C5_CLK - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI - - */
- GPIO_FUNC1, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP - - */
- GPIO_FUNC1, /* RESERVED GPIO_S0_SC[092] - - - */
- GPIO_FUNC1, /* RESERVED GPIO_S0_SC[093] - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[094] SIO_PWM[0] - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[095] SIO_PWM[1] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] - - - */
- GPIO_FUNC1, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] - - - */
- GPIO_DEFAULT, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] - - - */
- GPIO_END
-};
-
-/* SSUS GPIOs (GPIO_S5) */
-static const struct soc_gpio_map gpssus_gpio_map[] = {
- GPIO_DEFAULT, /* GPIO_S5[00] RESERVED - - - */
- GPIO_DEFAULT, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */
- GPIO_DEFAULT, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */
- GPIO_DEFAULT, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */
- GPIO_DEFAULT, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */
- GPIO_NC, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */
- GPIO_NC, /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */
- GPIO_NC, /* GPIO_S5[10] RESERVED RESERVED RESERVED - */
- GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - - */
- GPIO_FUNC0, /* PMC_SUSCLK[0] GPIO_S5[12] - - - */
- GPIO_FUNC1, /* RESERVED GPIO_S5[13] - - - */
- GPIO_FUNC1, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - - */
- GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - - */
- GPIO_FUNC0, /* PMC_PWRBTN# GPIO_S5[16] - - - */
- GPIO_DEFAULT, /* RESERVED GPIO_S5[17] - - - */
- GPIO_FUNC1, /* PMC_SUS_STAT# GPIO_S5[18] - - - */
- GPIO_FUNC0, /* USB_OC[0]# GPIO_S5[19] - - - */
- GPIO_FUNC0, /* USB_OC[1]# GPIO_S5[20] - - - */
- GPIO_FUNC0, /* PCU_SPI_CS[1]# GPIO_S5[21] - - - */
- GPIO_DEFAULT, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */
- GPIO_DEFAULT, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED - */
- GPIO_NC, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED - */
- GPIO_NC, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED - */
- GPIO_NC, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED - */
- GPIO_NC, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED - */
- GPIO_DEFAULT, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED - */
- GPIO_END
-};
-
-static struct soc_gpio_config gpio_config = {
- .ncore = gpncore_gpio_map,
- .score = gpscore_gpio_map,
- .ssus = gpssus_gpio_map,
- .core_dirq = NULL,
- .sus_dirq = NULL,
-};
-
-struct soc_gpio_config* mainboard_get_gpios(void)
-{
- return &gpio_config;
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.c b/src/mainboard/intel/bayleybay_fsp/irqroute.c
deleted file mode 100644
index db8c512a43..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h
deleted file mode 100644
index febbcc8257..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/irqroute.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
-
-/*
- *IR02h GFX INT(A) - PIRQ A
- *IR10h EMMC INT(ABCD) - PIRQ DEFG
- *IR11h SDIO INT(A) - PIRQ B
- *IR12h SD INT(A) - PIRQ C
- *IR13h SATA INT(A) - PIRQ D
- *IR14h XHCI INT(A) - PIRQ E
- *IR15h LP Audio INT(A) - PIRQ F
- *IR17h MMC INT(A) - PIRQ F
- *IR18h SIO INT(ABCD) - PIRQ BADC
- *IR1Ah TXE INT(A) - PIRQ F
- *IR1Bh HD Audio INT(A) - PIRQ G
- *IR1Ch PCIe INT(ABCD) - PIRQ EFGH
- *IR1Dh EHCI INT(A) - PIRQ D
- *IR1Eh SIO INT(ABCD) - PIRQ BDEF
- *IR1Fh LPC INT(ABCD) - PIRQ HGBC
- */
-
-/* PCIe bridge routing */
-#define BRIDGE1_DEV PCIE_DEV
-
-/* PCI bridge IRQs need to be updated in both tables and need to match */
-#define PCIE_BRIDGE_IRQ_ROUTES \
- PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
-
-/* Devices set as A, A, A, A evaluate as 0, and don't get set */
-#define PCI_DEV_PIRQ_ROUTES \
- PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
- PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
- PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
- PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
- PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
- PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
- PIRQ_PIC(A, 4), \
- PIRQ_PIC(B, 5), \
- PIRQ_PIC(C, 7), \
- PIRQ_PIC(D, 10), \
- PIRQ_PIC(E, 11), \
- PIRQ_PIC(F, 12), \
- PIRQ_PIC(G, 14), \
- PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c
deleted file mode 100644
index f6ba0355ee..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/mainboard.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#if CONFIG(VGA_ROM_RUN)
-#include <x86emu/x86emu.h>
-#endif
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
deleted file mode 100644
index a6ccd960b1..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stddef.h>
-#include <arch/cbfs.h>
-#include <cpu/x86/mtrr.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/lpc.h>
-#include <soc/pci_devs.h>
-#include <soc/romstage.h>
-#include <soc/baytrail.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry()
-{
-
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param fd_mask
- * @param fd2_mask
- */
-void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
-{
-
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry()
-{
-
-}
-
-const uint32_t mAzaliaVerbTableData13[] = {
-/*
- *ALC262 Verb Table - 10EC0262
- */
- /* Pin Complex (NID 0x11) */
- 0x01171CF0,
- 0x01171D11,
- 0x01171E11,
- 0x01171F41,
- /* Pin Complex (NID 0x12) */
- 0x01271CF0,
- 0x01271D11,
- 0x01271E11,
- 0x01271F41,
- /* Pin Complex (NID 0x14) */
- 0x01471C10,
- 0x01471D40,
- 0x01471E01,
- 0x01471F01,
- /* Pin Complex (NID 0x15) */
- 0x01571CF0,
- 0x01571D11,
- 0x01571E11,
- 0x01571F41,
- /* Pin Complex (NID 0x16) */
- 0x01671CF0,
- 0x01671D11,
- 0x01671E11,
- 0x01671F41,
- /* Pin Complex (NID 0x18) */
- 0x01871C20,
- 0x01871D98,
- 0x01871EA1,
- 0x01871F01,
- /* Pin Complex (NID 0x19) */
- 0x01971C21,
- 0x01971D98,
- 0x01971EA1,
- 0x01971F02,
- /* Pin Complex (NID 0x1A) */
- 0x01A71C2F,
- 0x01A71D30,
- 0x01A71E81,
- 0x01A71F01,
- /* Pin Complex (NID 0x1B) */
- 0x01B71C1F,
- 0x01B71D40,
- 0x01B71E21,
- 0x01B71F02,
- /* Pin Complex (NID 0x1C) */
- 0x01C71CF0,
- 0x01C71D11,
- 0x01C71E11,
- 0x01C71F41,
- /* Pin Complex (NID 0x1D) */
- 0x01D71C01,
- 0x01D71DC6,
- 0x01D71E14,
- 0x01D71F40,
- /* Pin Complex (NID 0x1E) */
- 0x01E71CF0,
- 0x01E71D11,
- 0x01E71E11,
- 0x01E71F41,
- /* Pin Complex (NID 0x1F) */
- 0x01F71CF0,
- 0x01F71D11,
- 0x01F71E11,
- 0x01F71F41 };
-
-const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { {
-/*
- * VerbTable: (RealTek ALC262)
- * Revision ID = 0xFF, support all steps
- * Codec Verb Table For AZALIA
- * Codec Address: CAd value (0/1/2)
- * Codec Vendor: 0x10EC0262
- */
- {
- 0x10EC0262, /* Vendor ID/Device IDA */
- 0x0000, /* SubSystem ID */
- 0xFF, /* Revision IDA */
- 0x01, /* Front panel support (1=yes, 2=no) */
- 0x000B, /* Number of Rear Jacks = 11 */
- 0x0002 /* Number of Front Jacks = 2 */
- },
- (uint32_t *)mAzaliaVerbTableData13 } };
-
-const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = {
- .Pme = 1,
- .DS = 1,
- .DA = 0,
- .HdmiCodec = 1,
- .AzaliaVCi = 1,
- .Rsvdbits = 0,
- .AzaliaVerbTableNum = 1,
- .AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE *)mAzaliaVerbTable,
- .ResetWaitTimer = 300 };
-
-/** /brief customize fsp parameters here if needed
- */
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
- UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
-
- /* Initialize the Azalia Verb Tables to mainboard specific version */
- UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
-
- /* Disable 2nd DIMM on Bakersport*/
-#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP)
- UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
-#endif
-}
diff --git a/src/mainboard/intel/bayleybay_fsp/thermal.h b/src/mainboard/intel/bayleybay_fsp/thermal.h
deleted file mode 100644
index 3973ca8fe9..0000000000
--- a/src/mainboard/intel/bayleybay_fsp/thermal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_THERMAL_H
-#define MAINBOARD_THERMAL_H
-
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 100
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 90
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 100
-
-#endif /* MAINBOARD_THERMAL_H */
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
deleted file mode 100644
index ca24c92aa6..0000000000
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_MINNOWMAX
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select SOC_INTEL_FSP_BAYTRAIL
- select BOARD_ROMSIZE_KB_8192
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
-
-config MAINBOARD_DIR
- string
- default "intel/minnowmax"
-
-config MAINBOARD_PART_NUMBER
- string
- default "Minnow Max"
-
-config MAX_CPUS
- int
- default 16
-
-config FSP_FILE
- string
- default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
-
-config CBFS_SIZE
- hex
- default 0x00300000
-
-config ENABLE_FSP_FAST_BOOT
- bool
- depends on HAVE_FSP_BIN
- default y
-
-config VIRTUAL_ROM_SIZE
- hex
- depends on ENABLE_FSP_FAST_BOOT
- default 0x800000
-
-config POST_DEVICE
- bool
- default n
-
-config VGA_BIOS
- bool
- default y if FSP_PACKAGE_DEFAULT
-
-endif # BOARD_INTEL_MINNOWMAX
diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name
deleted file mode 100644
index abe9225960..0000000000
--- a/src/mainboard/intel/minnowmax/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_MINNOWMAX
- bool "Minnow Max"
diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc
deleted file mode 100644
index 3074df2138..0000000000
--- a/src/mainboard/intel/minnowmax/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += gpio.c
-ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl
deleted file mode 100644
index b032ee189d..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
- Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c
deleted file mode 100644
index fe95a3106c..0000000000
--- a/src/mainboard/intel/minnowmax/acpi_tables.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include <soc/iomap.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- acpi_init_gnvs(gnvs);
-
- /* No TPM Present */
- gnvs->tpmp = 0;
-
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- current = acpi_madt_irq_overrides(current);
-
- return current;
-}
diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt
deleted file mode 100644
index 5af79f8de4..0000000000
--- a/src/mainboard/intel/minnowmax/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: sbc
-ROM protocol: SPI
-Flashrom support: y
-Release year: 2014
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
deleted file mode 100644
index 4cb5106191..0000000000
--- a/src/mainboard/intel/minnowmax/cmos.layout
+++ /dev/null
@@ -1,108 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392 3 r 0 unused
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-411 2 e 8 use_xhci_over_ehci
-#413 3 r 0 unused
-
-# MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-#save timestamps in pre-ram boot areas
-1720 64 h 0 timestamp_value1
-1784 64 h 0 timestamp_value2
-1848 64 h 0 timestamp_value3
-1912 64 h 0 timestamp_value4
-1976 64 h 0 timestamp_value5
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-8 0 EHCI
-8 1 XHCI
-8 2 Default
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
deleted file mode 100644
index 873b5898e7..0000000000
--- a/src/mainboard/intel/minnowmax/devicetree.cb
+++ /dev/null
@@ -1,93 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/fsp_baytrail
-
- #### ACPI Register Settings ####
- register "fadt_pm_profile" = "PM_UNSPECIFIED"
- register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
-
- #### FSP register settings ####
- register "PcdSataMode" = "SATA_MODE_AHCI"
- register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
- register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
- register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
- register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
- register "PcdGttSize" = "GTT_SIZE_DEFAULT"
- register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
- register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
- register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
- register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
- register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
- register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
- register "DRAMType" = "DRAM_TYPE_DDR3L"
- register "DIMM0Enable" = "DIMM0_ENABLE"
- register "DIMM1Enable" = "DIMM1_DISABLE"
- register "DIMMDWidth" = "DIMM_DWIDTH_X16"
- register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT
- register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
- register "DIMMSides" = "DIMM_SIDES_1RANK"
- register "DIMMtCL" = "11"
- register "DIMMtRPtRCD" = "11"
- register "DIMMtWR" = "12"
- register "DIMMtWTR" = "6"
- register "DIMMtRRD" = "6"
- register "DIMMtRTP" = "6"
- register "DIMMtFAW" = "20"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- device domain 0 on
- device pci 00.0 on end # 8086 0F00 - SoC router -
- device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
- device pci 03.0 off end # 8086 0F38 - MIPI -
-
- device pci 10.0 off end # 8086 0F14 - EMMC Port -
- device pci 11.0 off end # 8086 0F15 - SDIO Port -
- device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
- device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
- device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
- device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
- device pci 17.0 off end # 8086 0F50 - MMC Port -
- device pci 18.0 on end # 8086 0F40 - SIO - DMA -
- device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
- device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
- device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
- device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
- device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
- device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
- device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
- device pci 1a.0 on end # 8086 0F18 - TXE -
- device pci 1b.0 off end # 8086 0F04 - HD Audio -
- device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on
- device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)
- device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
- device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
- device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
- device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
- device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
- device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
- device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
- device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
- device pci 1e.5 on end # 8086 0F0E - SPI LSEC
- device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
- device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
- end
-end
diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl
deleted file mode 100644
index bea6af7973..0000000000
--- a/src/mainboard/intel/minnowmax/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define INCLUDE_LPE 1
-#define INCLUDE_SCC 1
-#define INCLUDE_EHCI 1
-#define INCLUDE_XHCI 1
-#define INCLUDE_LPSS 1
-
-
-#include <arch/acpi.h>
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0 and up
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/fsp_baytrail/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
-
- #include <cpu/intel/common/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
- }
- }
-
- /* Chipset specific sleep states */
- #include <southbridge/intel/common/acpi/sleepstates.asl>
-
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c
deleted file mode 100644
index 4194bfc324..0000000000
--- a/src/mainboard/intel/minnowmax/fadt.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- acpi_fill_in_fadt(fadt, facs, dsdt);
-
- /* Platform specific customizations go here */
-
- header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
deleted file mode 100644
index b0f78c8b57..0000000000
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <soc/gpio.h>
-#include "irqroute.h"
-
-/*
- * For multiplexed functions, look in EDS:
- * 10.3 Ball Name and Function by Location
- *
- * The pads list is in the BWG_VOL2 Rev1p2:
- * Note that Pad # is not the same as GPIO#
- * 37 GPIO Handling:
- * Table 37-1. SCORE Pads List
- * Table 37-2. SSUSORE Pads List
- */
-
-/* NCORE GPIOs */
-static const struct soc_gpio_map gpncore_gpio_map[] = {
- GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD
- GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT
- GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK
- GPIO_NC, // GPIO_S0_NC[03] - No Connect
- GPIO_NC, // GPIO_S0_NC[04] - No Connect
- GPIO_NC, // GPIO_S0_NC[05] - No Connect
- GPIO_NC, // GPIO_S0_NC[06] - No Connect
- GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT
- GPIO_NC, // GPIO_S0_NC[08] - No Connect
- GPIO_NC, // GPIO_S0_NC[09] - No Connect
- GPIO_NC, // GPIO_S0_NC[10] - No Connect
- GPIO_NC, // GPIO_S0_NC[11] - No Connect
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15
- GPIO_NC, // GPIO_S0_NC[13] - No Connect
- GPIO_NC, // GPIO_S0_NC[14] - No Connect
- GPIO_NC, // GPIO_S0_NC[15] - No Connect
- GPIO_NC, // GPIO_S0_NC[16] - No Connect
- GPIO_NC, // GPIO_S0_NC[17] - No Connect
- GPIO_NC, // GPIO_S0_NC[18] - No Connect
- GPIO_NC, // GPIO_S0_NC[19] - No Connect
- GPIO_NC, // GPIO_S0_NC[20] - No Connect
- GPIO_NC, // GPIO_S0_NC[21] - No Connect
- GPIO_NC, // GPIO_S0_NC[22] - No Connect
- GPIO_NC, // GPIO_S0_NC[23] - No Connect
- GPIO_NC, // GPIO_S0_NC[24] - No Connect
- GPIO_NC, // GPIO_S0_NC[25] - No Connect
- GPIO_NC, // GPIO_S0_NC[26] - No Connect
- GPIO_END
-};
-
-/* SCORE GPIOs (GPIO_S0_SC_XX) */
-static const struct soc_gpio_map gpscore_gpio_map[] = {
- GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0
- GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1
- GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B
- GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0
- GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1
- GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2
- GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3
- GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP
- GPIO_NC, // GPIO_S0_SC[008] - No Connect
- GPIO_NC, // GPIO_S0_SC[009] - No Connect
- GPIO_NC, // GPIO_S0_SC[010] - No Connect
- GPIO_NC, // GPIO_S0_SC[011] - No Connect
- GPIO_NC, // GPIO_S0_SC[012] - No Connect
- GPIO_NC, // GPIO_S0_SC[013] - No Connect
- GPIO_NC, // GPIO_S0_SC[014] - No Connect
- GPIO_NC, // GPIO_S0_SC[015] - No Connect
- GPIO_NC, // GPIO_S0_SC[016] - No Connect
- GPIO_NC, // GPIO_S0_SC[017] - No Connect
- GPIO_NC, // GPIO_S0_SC[018] - No Connect
- GPIO_NC, // GPIO_S0_SC[019] - No Connect
- GPIO_NC, // GPIO_S0_SC[020] - No Connect
- GPIO_NC, // GPIO_S0_SC[021] - No Connect
- GPIO_NC, // GPIO_S0_SC[022] - No Connect
- GPIO_NC, // GPIO_S0_SC[023] - No Connect
- GPIO_NC, // GPIO_S0_SC[024] - No Connect
- GPIO_NC, // GPIO_S0_SC[025] - No Connect
- GPIO_NC, // GPIO_S0_SC[026] - No Connect
- GPIO_NC, // GPIO_S0_SC[027] - No Connect
- GPIO_NC, // GPIO_S0_SC[028] - No Connect
- GPIO_NC, // GPIO_S0_SC[029] - No Connect
- GPIO_NC, // GPIO_S0_SC[030] - No Connect
- GPIO_NC, // GPIO_S0_SC[031] - No Connect
- GPIO_NC, // GPIO_S0_SC[032] - No Connect
- GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK
- GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0
- GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1
- GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2
- GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3
- GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD#
- GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD
- GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN)
- GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN)
- GPIO_NC, // GPIO_S0_SC[042] - No Connect
- GPIO_NC, // GPIO_S0_SC[043] - No Connect
- GPIO_NC, // GPIO_S0_SC[044] - No Connect
- GPIO_NC, // GPIO_S0_SC[045] - No Connect
- GPIO_NC, // GPIO_S0_SC[046] - No Connect
- GPIO_NC, // GPIO_S0_SC[047] - No Connect
- GPIO_NC, // GPIO_S0_SC[048] - No Connect
- GPIO_NC, // GPIO_S0_SC[049] - No Connect
- GPIO_NC, // GPIO_S0_SC[050] - No Connect
- GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA
- GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK
- GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT
- GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55)
- GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56
- GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58)
- GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB
- GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB
- GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD
- GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK
- GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM
- GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN
- GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT
- GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1
- GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO
- GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI
- GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK
- GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD
- GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD
- GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB
- GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB
- GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD
- GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD
- GPIO_NC, // GPIO_S0_SC[076] - No Connect
- GPIO_NC, // GPIO_S0_SC[077] - No Connect
- GPIO_NC, // GPIO_S0_SC[078] - No Connect
- GPIO_NC, // GPIO_S0_SC[079] - No Connect
- GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA)
- GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL)
- GPIO_NC, // GPIO_S0_SC[082] - No Connect
- GPIO_NC, // GPIO_S0_SC[083] - No Connect
- GPIO_NC, // GPIO_S0_SC[084] - No Connect
- GPIO_NC, // GPIO_S0_SC[085] - No Connect
- GPIO_NC, // GPIO_S0_SC[086] - No Connect
- GPIO_NC, // GPIO_S0_SC[087] - No Connect
- GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA
- GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL
- GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA
- GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL
- GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13
- GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16
- GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0
- GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1
- GPIO_NC, // GPIO_S0_SC[096] - No Connect
- GPIO_NC, // GPIO_S0_SC[097] - No Connect
- GPIO_NC, // GPIO_S0_SC[098] - No Connect
- GPIO_NC, // GPIO_S0_SC[099] - No Connect
- GPIO_NC, // GPIO_S0_SC[100] - No Connect
- GPIO_NC, // GPIO_S0_SC[101] - No Connect
- GPIO_END
-};
-
-/* SSUS GPIOs (GPIO_S5) */
-static const struct soc_gpio_map gpssus_gpio_map[] = {
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2
- GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB
- GPIO_NC, // GPIO_S5[04] - No Connect
- GPIO_INPUT, // GPIO_S5[05] - BOM_OP1
- // Memory: 0=1GB 1=2GB or 4GB
- GPIO_INPUT, // GPIO_S5[06] - BOM_OP2
- GPIO_INPUT, // GPIO_S5[07] - BOM_OP3
- GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0
- GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1
- GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK
- GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14)
- GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0
- GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10)
- GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20
- GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R
- GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN
- GPIO_NC, // GPIO_S5[17] - No Connect
- GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7)
- GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0
- GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1
- GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B
- GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3
- GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4
- GPIO_NC, // GPIO_S5[31] - No Connect
- GPIO_NC, // GPIO_S5[32] - No Connect
- GPIO_NC, // GPIO_S5[33] - No Connect
- GPIO_NC, // GPIO_S5[34] - No Connect
- GPIO_NC, // GPIO_S5[35] - No Connect
- GPIO_NC, // GPIO_S5[36] - No Connect
- GPIO_NC, // GPIO_S5[37] - No Connect
- GPIO_NC, // GPIO_S5[38] - No Connect
- GPIO_NC, // GPIO_S5[39] - No Connect
- GPIO_NC, // GPIO_S5[40] - No Connect
- GPIO_NC, // GPIO_S5[41] - No Connect
- GPIO_NC, // GPIO_S5[42] - No Connect
- GPIO_NC, // GPIO_S5[43] - No Connect
- GPIO_END
-};
-
-static struct soc_gpio_config gpio_config = {
- .ncore = gpncore_gpio_map,
- .score = gpscore_gpio_map,
- .ssus = gpssus_gpio_map,
- .core_dirq = NULL,
- .sus_dirq = NULL,
-};
-
-struct soc_gpio_config *mainboard_get_gpios(void)
-{
- return &gpio_config;
-}
diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c
deleted file mode 100644
index db8c512a43..0000000000
--- a/src/mainboard/intel/minnowmax/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h
deleted file mode 100644
index 20281b7e3f..0000000000
--- a/src/mainboard/intel/minnowmax/irqroute.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
-
-/*
- *IR02h GFX INT(A) - PIRQ A
- *IR10h EMMC INT(ABCD) - PIRQ DEFG
- *IR11h SDIO INT(A) - PIRQ B
- *IR12h SD INT(A) - PIRQ C
- *IR13h SATA INT(A) - PIRQ D
- *IR14h XHCI INT(A) - PIRQ E
- *IR15h LP Audio INT(A) - PIRQ F
- *IR17h MMC INT(A) - PIRQ F
- *IR18h SIO INT(ABCD) - PIRQ BADC
- *IR1Ah TXE INT(A) - PIRQ F
- *IR1Bh HD Audio INT(A) - PIRQ G
- *IR1Ch PCIe INT(ABCD) - PIRQ EFGH
- *IR1Dh EHCI INT(A) - PIRQ D
- *IR1Eh SIO INT(ABCD) - PIRQ BDEF
- *IR1Fh LPC INT(ABCD) - PIRQ HGBC
- */
-
-/* PCIe bridge routing */
-#define BRIDGE1_DEV PCIE_DEV
-
-/* PCI bridge IRQs need to be updated in both tables and need to match */
-#define PCIE_BRIDGE_IRQ_ROUTES \
- PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
-
-/* Devices set as A, A, A, A evaluate as 0, and don't get set */
-#define PCI_DEV_PIRQ_ROUTES \
- PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \
- PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
- PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
- PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
- PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
- PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
- PIRQ_PIC(A, 3), \
- PIRQ_PIC(B, 5), \
- PIRQ_PIC(C, 7), \
- PIRQ_PIC(D, 10), \
- PIRQ_PIC(E, 11), \
- PIRQ_PIC(F, 12), \
- PIRQ_PIC(G, 14), \
- PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c
deleted file mode 100644
index 0fe1259420..0000000000
--- a/src/mainboard/intel/minnowmax/mainboard.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-}
-
-/*
- * mainboard_final is executed as one of the last items before loading the
- * payload.
- *
- * This is the latest point to add customization.
- */
-static void mainboard_final(void *chip_info)
-{
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
- .final = mainboard_final,
-};
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
deleted file mode 100644
index 38b7e0d6ff..0000000000
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Intel Corporation
- * Copyright (C) 2018 CMR Surgical Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/romstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <soc/gpio.h>
-#include <soc/intel/fsp_baytrail/chip.h>
-#include <cpu/x86/tsc.h>
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param fd_mask
- * @param fd2_mask
- */
-void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
-{
-
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-
-}
-
-/* Set up the default soldered down memory config for 1GB */
-static const MEMORY_DOWN_DATA minnowmax_memory_config[] = {
- /* 1066 */
- {
- .EnableMemoryDown = 1,
- .DRAMSpeed = 1, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
- .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
- .DIMM0Enable = 1, /* DIMM 0 Enable */
- .DIMM1Enable = 0, /* DIMM 1 Enable */
- .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
- .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
- .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
- .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */
- .DIMMtCL = 11, /* tCL */
- .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
- .DIMMtWR = 12, /* tWR in DRAM clk */
- .DIMMtWTR = 6, /* tWTR in DRAM clk */
- .DIMMtRRD = 6, /* tRRD in DRAM clk */
- .DIMMtRTP = 6, /* tRTP in DRAM clk */
- .DIMMtFAW = 20, /* tFAW in DRAM clk */
- },
- /* 1333 */
- {
- .EnableMemoryDown = 1,
- .DRAMSpeed = 2, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
- .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
- .DIMM0Enable = 1, /* DIMM 0 Enable */
- .DIMM1Enable = 0, /* DIMM 1 Enable */
- .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
- .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
- .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
- .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */
- .DIMMtCL = 9, /* tCL */
- .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
- .DIMMtWR = 10, /* tWR in DRAM clk */
- .DIMMtWTR = 5, /* tWTR in DRAM clk */
- .DIMMtRRD = 4, /* tRRD in DRAM clk */
- .DIMMtRTP = 5, /* tRTP in DRAM clk */
- .DIMMtFAW = 30, /* tFAW in DRAM clk */
- }
-};
-
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
- UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
- u8 use_xhci = UpdData->PcdEnableXhci;
- u8 gpio5 = 0;
- int is_1333_sku;
-
- /*
- * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's
- * no good way of knowing the SKU'ing so frequency is used as a proxy.
- * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the
- * E3827 and E3845 are 1750MHz and 1910MHz, respectively.
- */
- is_1333_sku = !!(tsc_freq_mhz() >= 1700);
-
- printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n",
- is_1333_sku ? 1333 : 1066);
-
- /* Set up soldered down memory parameters for 1GB */
- UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku];
-
- /*
- * Minnow Max Board
- * Read SSUS gpio 5 to determine memory type
- * 0 : 1GB SKU uses 2Gb density memory
- * 1 : 2GB SKU uses 4Gb density memory
- *
- * devicetree.cb assumes 1GB SKU board
- */
- configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
- gpio5 = read_ssus_gpio(5);
- if (gpio5)
- UpdData->PcdMemoryParameters.DIMMDensity
- += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
- printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n",
- gpio5 ? "2 / 4" : "1");
- /* Update XHCI UPD value if required */
- get_option(&use_xhci, "use_xhci_over_ehci");
- if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
- UpdData->PcdEnableXhci = use_xhci;
- printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
- UpdData->PcdEnableXhci?"Enabled":"Disabled");
- }
-}