summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorJohn Zhao <john.zhao@intel.com>2020-06-30 17:36:24 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-12 19:31:01 +0000
commit23d3ad0f640c32a452cc36eb3040f324feeee3e8 (patch)
tree67d48f7afd89e9af8067d06b26e7465ec3d671bf /src/mainboard/intel
parentef079c86ea3c24dd30d1bbad2e446632ec1c0104 (diff)
downloadcoreboot-23d3ad0f640c32a452cc36eb3040f324feeee3e8.tar.xz
mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4
This change enables s0ix for tglrvp up3 and up4 platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb3
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 612a97d201..b4a121a95a 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -114,6 +114,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 7a97ad9098..b08cd3c119 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -110,6 +110,9 @@ chip soc/intel/tigerlake
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"