chromeos: update old boards to use lb_add_gpios notation

Instead of manually filling out the lb_gpios struct,
use the newer lb_add_gpios notation, which is more
compact and less error-prone.

BUG=b:124141368
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none

Change-Id: I90795f32be5de881c94519933f36127098c184df
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 34 insertions, 82 deletions

diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 1c62e5e0eb..875578fed4 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -26,52 +26,25 @@
 #if ENV_RAMSTAGE
 #include <boot/coreboot_tables.h>
 
-#define GPIO_COUNT	6
-
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	struct device *dev = pcidev_on_root(0x1f, 0);
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
-	if (!gpio_base)
-		return;
-
-	u32 gp_lvl  = inl(gpio_base + GP_LVL);
-	u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
-	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
-	gpios->count = GPIO_COUNT;
-
-	/* Write Protect: GPIO22 */
-	gpios->gpios[0].port = 0;
-	gpios->gpios[0].polarity = ACTIVE_LOW;
-	gpios->gpios[0].value = (gp_lvl >> 22) & 1;
-	strncpy((char *)gpios->gpios[0].name,"write protect",
-							GPIO_MAX_NAME_LENGTH);
+	struct lb_gpio chromeos_gpios[] = {
+		/* Write Protect: GPIO22 */
+		{0, ACTIVE_LOW, get_write_protect_state(), "write protect"},
 
-	/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
-	gpios->gpios[1].port = 69;
-	gpios->gpios[1].polarity = ACTIVE_HIGH;
-	gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1;
-	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+		/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
+		{69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
 
-	/* Hard code the lid switch GPIO to open. */
-	gpios->gpios[3].port = -1;
-	gpios->gpios[3].polarity = ACTIVE_HIGH;
-	gpios->gpios[3].value = 1;
-	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+		/* Hard code the lid switch GPIO to open. */
+		{-1, ACTIVE_HIGH, 1, "lid"},
 
-	/* Power Button */
-	gpios->gpios[4].port = -1;
-	gpios->gpios[4].polarity = ACTIVE_HIGH;
-	gpios->gpios[4].value = 0;
-	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+		/* Power Button */
+		{-1, ACTIVE_HIGH, 0, "power"},
 
-	/* Did we load the VGA option ROM? */
-	gpios->gpios[5].port = -1;
-	gpios->gpios[5].polarity = ACTIVE_HIGH;
-	gpios->gpios[5].value = gfx_get_init_done();
-	strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+		/* Did we load the VGA option ROM? */
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 #endif
 
@@ -86,7 +59,8 @@ int get_recovery_mode_switch(void)
 
 int get_write_protect_state(void)
 {
-	return 0;
+	/* Write protect is active low, so invert it here */
+	return !get_gpio(22);
 }
 
 static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 8c0aeea4d1..9fae82211f 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -26,53 +26,25 @@
 #if ENV_RAMSTAGE
 #include <boot/coreboot_tables.h>
 
-#define GPIO_COUNT	6
-
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
-	struct device *dev = pcidev_on_root(0x1f, 0);
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
-	if (!gpio_base)
-		return;
-
-	u32 gp_lvl = inl(gpio_base + 0x0c);
-	u32 gp_lvl2 = inl(gpio_base + 0x38);
-	/* u32 gp_lvl3 = inl(gpio_base + 0x48); */
-
-	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
-	gpios->count = GPIO_COUNT;
+	struct lb_gpio chromeos_gpios[] = {
+		/* Write Protect: GPIO48 */
+		{48, ACTIVE_LOW, get_write_protect_state(), "write protect"},
 
-	/* Write Protect: GPIO48 */
-	gpios->gpios[0].port = 48;
-	gpios->gpios[0].polarity = ACTIVE_LOW;
-	gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1;
-	strncpy((char *)gpios->gpios[0].name,"write protect",
-							GPIO_MAX_NAME_LENGTH);
+		/* Recovery: GPIO22 */
+		{22, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"},
 
-	/* Recovery: GPIO22 */
-	gpios->gpios[1].port = 22;
-	gpios->gpios[1].polarity = ACTIVE_LOW;
-	gpios->gpios[1].value = (gp_lvl >> 22) & 1;
-	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+		/* Hard code the lid switch GPIO to open. */
+		{-1, ACTIVE_HIGH, 1, "lid"},
 
-	/* Hard code the lid switch GPIO to open. */
-	gpios->gpios[3].port = -1;
-	gpios->gpios[3].polarity = ACTIVE_HIGH;
-	gpios->gpios[3].value = 1;
-	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+		/* Power Button */
+		{-1, ACTIVE_HIGH, 0, "power"},
 
-	/* Power Button */
-	gpios->gpios[4].port = -1;
-	gpios->gpios[4].polarity = ACTIVE_HIGH;
-	gpios->gpios[4].value = 0;
-	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
-
-	/* Did we load the VGA option ROM? */
-	gpios->gpios[5].port = -1;
-	gpios->gpios[5].polarity = ACTIVE_HIGH;
-	gpios->gpios[5].value = gfx_get_init_done();
-	strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+		/* Did we load the VGA option ROM? */
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 #endif
 
@@ -82,6 +54,12 @@ int get_recovery_mode_switch(void)
 	return !get_gpio(22);
 }
 
+int get_write_protect_state(void)
+{
+	/* Write protect is active low, so invert it here */
+	return !get_gpio(48);
+}
+
 static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
 	CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),