mb/intel/coffeelake_rvp: Switch to overridetree setup

This patch moves the common devicetree settings into baseboard and
creates overridetree.cb for each variant. For PCIe root port settings,
SATA, eMMC, I2Cs and GBe, they are in overridetree.

TEST=build an image for each variant

Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 171 insertions, 301 deletions

diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 72906d7d3e..da2cd2eb3d 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -59,7 +59,11 @@ config UART_FOR_CONSOLE
 
 config DEVICETREE
 	string
-	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+	default "variants/baseboard/devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config FMDFILE
 	string
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
index 429d5daca8..01d970ca56 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -7,20 +7,9 @@ chip soc/intel/cannonlake
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "ScsEmmcHs400Enabled" = "1"
-	register "HeciEnabled" = "1"
 
-        # Enable eDP device
-        register "DdiPortEdp" = "1"
-        # Enable HPD for DDI ports B/C/D/F
-        register "DdiPortBHpd" = "1"
-        register "DdiPortCHpd" = "1"
-        register "DdiPortDHpd" = "1"
-        register "DdiPortFHpd" = "1"
-        # Enable DDC for DDI ports B/C/D/F
-        register "DdiPortBDdc" = "1"
-        register "DdiPortCDdc" = "1"
-        register "DdiPortDDdc" = "1"
-        register "DdiPortFDdc" = "1"
+	# HECI
+	register "HeciEnabled" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
@@ -40,36 +29,9 @@ chip soc/intel/cannonlake
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
 
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsEnable[3]" = "1"
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHda" = "1"
 
-	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[1]" = "1"
-	register "PcieRpEnable[2]" = "1"
-	register "PcieRpEnable[3]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
-
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
 	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
@@ -87,8 +49,8 @@ chip soc/intel/cannonlake
 	# Enable "Intel Speed Shift Technology"
 	register "speed_shift_enable" = "1"
 
-	# GPIO for SD card detect
-	register "sdcard_cd_gpio" = "GPP_G5"
+	# Disable S0ix
+	register "s0ix_enable" = "0"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
@@ -99,41 +61,14 @@ chip soc/intel/cannonlake
 		device pci 12.6 off end # GSPI #2
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
-		chip drivers/intel/wifi
-			register "wake" = "PME_B0_EN_BIT"
-			device pci 14.3 on  end # CNVi wifi
-		end
 		device pci 14.5 on  end # SDCard
-		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
-		device pci 15.2 off end # I2C #2
-		device pci 15.3 off end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 on  end # SATA
-		device pci 19.0 on  end # I2C #4
-		device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
-		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13
-		device pci 1d.5 off end # PCI Express Port 14
-		device pci 1d.6 off end # PCI Express Port 15
-		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
 		device pci 1f.0 on
@@ -146,6 +81,5 @@ chip soc/intel/cannonlake
 		device pci 1f.3 on  end # Intel HDA
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 on  end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
index 9648ac345b..989b5cd4ea 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
@@ -5,9 +5,7 @@ chip soc/intel/cannonlake
 	end
 
 	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
 	register "RMT" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC6)"
@@ -53,25 +51,25 @@ chip soc/intel/cannonlake
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
 	register "PcieRpEnable[8]" = "1"
 	register "PcieRpEnable[9]" = "1"
 	register "PcieRpEnable[10]" = "1"
 	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
-	register "PcieRpEnable[16]" = "1"
-	register "PcieRpEnable[17]" = "1"
-	register "PcieRpEnable[18]" = "1"
-	register "PcieRpEnable[19]" = "1"
-	register "PcieRpEnable[20]" = "1"
-	register "PcieRpEnable[21]" = "1"
-	register "PcieRpEnable[22]" = "1"
-	register "PcieRpEnable[23]" = "1"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
+	register "PcieRpEnable[16]" = "0"
+	register "PcieRpEnable[17]" = "0"
+	register "PcieRpEnable[18]" = "0"
+	register "PcieRpEnable[19]" = "0"
+	register "PcieRpEnable[20]" = "0"
+	register "PcieRpEnable[21]" = "0"
+	register "PcieRpEnable[22]" = "0"
+	register "PcieRpEnable[23]" = "0"
 
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
@@ -91,34 +89,14 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[8]" = "8"
 	register "PcieClkSrcClkReq[9]" = "9"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
-	# HECI
-	register "HeciEnabled" = "1"
-
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on  end # SATA
-		device pci 19.0 off end # I2C #4
+		device pci 19.0 off end # I2C #4 (Not available on PCH-H)
+		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
@@ -127,27 +105,21 @@ chip soc/intel/cannonlake
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
 		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1d.4 off end # PCI Express Port 13
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
+		device pci 1b.0 off end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 off end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 on  end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index 126cab01f0..a63d4c0364 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -5,9 +5,7 @@ chip soc/intel/cannonlake
 	end
 
 	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
 	register "RMT" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
@@ -53,17 +51,17 @@ chip soc/intel/cannonlake
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
 	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
+	register "PcieRpEnable[9]" = "0"
+	register "PcieRpEnable[10]" = "0"
+	register "PcieRpEnable[11]" = "0"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
 	register "PcieRpEnable[16]" = "1"
 	register "PcieRpEnable[17]" = "1"
 	register "PcieRpEnable[18]" = "1"
@@ -95,38 +93,18 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[9]" = "9"
 	register "PcieClkSrcClkReq[10]" = "10"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
-	# HECI
-	register "HeciEnabled" = "1"
-
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
 		chip drivers/intel/wifi
 			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
 		end
-		device pci 14.5 on  end # SDCard
-		device pci 15.0 on  end # I2C 0
+		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 on  end # I2C #2
 		device pci 15.3 on  end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on  end # SATA
-		device pci 19.0 off end # I2C #4
+		device pci 19.0 off end # I2C #4 (Not available on PCH-H)
+		device pci 19.1 off end # I2C #5 (Not available on PCH-H)
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
 		device pci 1c.0 on  end # PCI Express Port 1
@@ -134,7 +112,7 @@ chip soc/intel/cannonlake
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9  X4 SLOT 1
+		device pci 1d.0 on  end # PCI Express Port 9 x4 SLOT 1
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
@@ -143,21 +121,11 @@ chip soc/intel/cannonlake
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
 		device pci 1b.0 on  end # PCI Express Port 17
+		device pci 1b.1 on  end # PCI Express Port 18
+		device pci 1b.2 on  end # PCI Express Port 19
+		device pci 1b.3 on  end # PCI Express Port 20
 		device pci 1b.4 on  end # PCI Express Port 21 X4 SLOT 2
-		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 on  end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
index e5f867cbdc..c5c291df9f 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
@@ -4,28 +4,6 @@ chip soc/intel/cannonlake
 		device lapic 0 on end
 	end
 
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "ScsEmmcHs400Enabled" = "1"
-
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
-
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHda" = "1"
 
@@ -34,17 +12,17 @@ chip soc/intel/cannonlake
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
 	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
+	register "PcieRpEnable[9]" = "0"
+	register "PcieRpEnable[10]" = "0"
+	register "PcieRpEnable[11]" = "0"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
 
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
@@ -60,9 +38,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"
 
@@ -86,19 +61,10 @@ chip soc/intel/cannonlake
 	}"
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
 		chip drivers/intel/wifi
 			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
 		end
-		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
@@ -113,13 +79,7 @@ chip soc/intel/cannonlake
 				device i2c 32 on end
 			end
 		end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off  end # SATA
+		device pci 17.0 off end # SATA
 		device pci 19.0 on  end # I2C #4
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
@@ -137,20 +97,9 @@ chip soc/intel/cannonlake
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0
 		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 off end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
index 241ac33345..93b5af9394 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
@@ -4,12 +4,6 @@ chip soc/intel/cannonlake
 		device lapic 0 on end
 	end
 
-	# FSP configuration
-	register "SaGv" = "SaGv_Enabled"
-	register "ScsEmmcHs400Enabled" = "1"
-	register "HeciEnabled" = "1"
-	register "s0ix_enable" = "1"
-
 	# Enable eDP device
 	register "DdiPortEdp" = "1"
 	# Enable HPD for DDI ports B/C
@@ -38,24 +32,6 @@ chip soc/intel/cannonlake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
-
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
-
 	register "SataSalpSupport" = "1"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
@@ -74,17 +50,17 @@ chip soc/intel/cannonlake
 	register "PcieRpEnable[2]" = "1"
 	register "PcieRpEnable[3]" = "1"
 	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[5]" = "1"
-	register "PcieRpEnable[6]" = "1"
-	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
 	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[9]" = "1"
-	register "PcieRpEnable[10]" = "1"
-	register "PcieRpEnable[11]" = "1"
-	register "PcieRpEnable[12]" = "1"
-	register "PcieRpEnable[13]" = "1"
-	register "PcieRpEnable[14]" = "1"
-	register "PcieRpEnable[15]" = "1"
+	register "PcieRpEnable[9]" = "0"
+	register "PcieRpEnable[10]" = "0"
+	register "PcieRpEnable[11]" = "0"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
 
 	register "PcieClkSrcUsage[0]" = "1"
 	register "PcieClkSrcUsage[1]" = "8"
@@ -100,43 +76,26 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # SA Thermal device
-		device pci 12.0 on  end # Thermal Subsystem
-		device pci 12.5 off end # UFS SCS
-		device pci 12.6 off end # GSPI #2
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
 		chip drivers/intel/wifi
 			register "wake" = "PME_B0_EN_BIT"
 			device pci 14.3 on  end # CNVi wifi
 		end
 		device pci 14.5 on  end # SDCard
 		device pci 15.0 on  end # I2C #0
-		device pci 15.1 on  end # I2C #1
+        device pci 15.1 on  end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 16.5 off end # Management Engine Interface 4
 		device pci 17.0 on  end # SATA
 		device pci 19.0 on  end # I2C #4
 		device pci 19.1 off end # I2C #5
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
-		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+        device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
@@ -148,20 +107,7 @@ chip soc/intel/cannonlake
 		device pci 1d.5 off end # PCI Express Port 14
 		device pci 1d.6 off end # PCI Express Port 15
 		device pci 1d.7 off end # PCI Express Port 16
-		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 on  end # GbE
 	end
 end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
new file mode 100644
index 0000000000..1e388240a6
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
@@ -0,0 +1,97 @@
+chip soc/intel/cannonlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C/D/F
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	register "DdiPortDHpd" = "1"
+	register "DdiPortFHpd" = "1"
+	# Enable DDC for DDI ports B/C/D/F
+	register "DdiPortBDdc" = "1"
+	register "DdiPortCDdc" = "1"
+	register "DdiPortDDdc" = "1"
+	register "DdiPortFDdc" = "1"
+
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "1"
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "0"
+	register "PcieRpEnable[6]" = "0"
+	register "PcieRpEnable[7]" = "0"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[9]" = "0"
+	register "PcieRpEnable[10]" = "0"
+	register "PcieRpEnable[11]" = "0"
+	register "PcieRpEnable[12]" = "0"
+	register "PcieRpEnable[13]" = "0"
+	register "PcieRpEnable[14]" = "0"
+	register "PcieRpEnable[15]" = "0"
+
+	register "PcieClkSrcUsage[0]" = "1"
+	register "PcieClkSrcUsage[1]" = "8"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+	register "PcieClkSrcUsage[3]" = "13"
+	register "PcieClkSrcUsage[4]" = "4"
+	register "PcieClkSrcUsage[5]" = "14"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	device domain 0 on
+		chip drivers/intel/wifi
+			register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		end
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 17.0 on  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.1 off end # UART #1
+		device pci 1f.6 on  end # GbE
+	end
+end