summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-03 13:05:10 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-09 16:23:16 +0000
commit6e1c471f701b8ba1e9c07a87ecc73c8d855478dd (patch)
treed0dad464e0d99f807bb7e0f183f76170fbd3f02c /src/mainboard/intel
parent2cb3cc52380818c8301a7cd6f9a1295147d01186 (diff)
downloadcoreboot-6e1c471f701b8ba1e9c07a87ecc73c8d855478dd.tar.xz
haswell: Turn RCBA configuration into a function
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c42
1 files changed, 20 insertions, 22 deletions
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 50499eaa19..58c684d98b 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -9,7 +9,8 @@
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
-const struct rcba_config_instruction rcba_config[] = {
+void mainboard_config_rcba(void)
+{
/*
* GFX INTA -> PIRQA (MSI)
* D28IP_P1IP WLAN INTA -> PIRQB
@@ -23,28 +24,26 @@ const struct rcba_config_instruction rcba_config[] = {
*/
/* Device interrupt pin register (board specific) */
- RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
- RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)),
- RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
- RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP)),
- RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
- RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
- RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)),
- RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+ (INTB << D28IP_P4IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
/* Device interrupt route registers */
- RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)),
- RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)),
- RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)),
- RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)),
- RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
- RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
- RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
-
- RCBA_END_CONFIG,
-};
+ RCBA32(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA);
+ RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG);
+ RCBA32(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE);
+ RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB);
+ RCBA32(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH);
+ RCBA32(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+ RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+}
void mainboard_romstage_entry(void)
{
@@ -116,7 +115,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
- .rcba_config = &rcba_config[0],
.copy_spd = NULL,
};