summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorVaibhav Shankar <vaibhav.shankar@intel.com>2017-10-11 17:37:53 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-12 18:26:38 +0000
commitb4e275f97bc5221b98b91bb5b54f088d07570a57 (patch)
tree54a5dd27dde363eea8ea0cb531d6ade279bc37f7 /src/mainboard/intel
parent4df1c4cedb51a0e7b249f1af239be30600e9199e (diff)
downloadcoreboot-b4e275f97bc5221b98b91bb5b54f088d07570a57.tar.xz
mainboard/intel/cannonlake_rvp: Add Sleep states
Add sleep state to DSDT table. Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/dsdt.asl4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 9f19cfb3ac..46d41e1656 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -39,4 +39,8 @@ DefinitionBlock(
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
+
+ // Chipset specific sleep states
+ #include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
}