diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-07-27 17:34:45 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-02 18:12:24 +0200 |
| commit | c31ba0ef529ef571ea839572f2c701a871cb33d7 (patch) | |
| tree | 32b38059ace1ce791edabe57ddd8f4056776258c /src/mainboard/intel | |
| parent | e96543e1fa3510a735d6de391b89ac350f56d287 (diff) | |
| download | coreboot-c31ba0ef529ef571ea839572f2c701a871cb33d7.tar.xz | |
drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/amenia/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/apollolake_rvp/romstage.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c index d08b343823..582c7542f6 100644 --- a/src/mainboard/intel/amenia/romstage.c +++ b/src/mainboard/intel/amenia/romstage.c @@ -17,7 +17,7 @@ #include <soc/romstage.h> #include <string.h> -#include <soc/fsp/FspmUpd.h> +#include <fsp/soc_binding.h> /* Channel 0 PHY to DUnit DQ mapping */ static const uint8_t swizzling_ch0_amenia[] = { @@ -43,7 +43,7 @@ static const uint8_t swizzling_ch3_amenia[] = { 17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30, }; -static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg) +static void amenia_fill_memory_params(FSP_M_CONFIG *cfg) { cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */ cfg->DIMM0SPDAddress = 0; @@ -87,9 +87,9 @@ static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg) sizeof(swizzling_ch3_amenia)); } -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +void mainboard_memory_init_params(FSPM_UPD *memupd) { - struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + FSP_M_CONFIG *cfg = &memupd->FspmConfig; cfg->Package = 1; /* 0x1:BGA */ cfg->MemoryDown = 1; diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index 0711501ee4..631adea496 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -18,7 +18,7 @@ #include <soc/romstage.h> #include <string.h> #include <fsp/api.h> -#include <soc/fsp/FspmUpd.h> +#include <fsp/soc_binding.h> static const uint8_t swizzling_rvp1[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, @@ -45,7 +45,7 @@ static const uint8_t swizzling3_rvp2[] = { 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, }; -static void rvp1_fill_memory_params(struct FSPM_UPD *mupd) +static void rvp1_fill_memory_params(FSPM_UPD *mupd) { mupd->FspmConfig.Profile = 33; mupd->FspmConfig.DIMM0SPDAddress = 0xa0; @@ -72,7 +72,7 @@ static void rvp1_fill_memory_params(struct FSPM_UPD *mupd) memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); } -static void rvp2_fill_memory_params(struct FSPM_UPD *mupd) +static void rvp2_fill_memory_params(FSPM_UPD *mupd) { mupd->FspmConfig.Profile = 5; mupd->FspmConfig.DIMM0SPDAddress = 0; @@ -103,7 +103,7 @@ static void rvp2_fill_memory_params(struct FSPM_UPD *mupd) sizeof(swizzling3_rvp2)); } -void mainboard_memory_init_params(struct FSPM_UPD *mupd) +void mainboard_memory_init_params(FSPM_UPD *mupd) { mupd->FspmConfig.Package = 0; mupd->FspmConfig.MemoryDown = 1; |