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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 20:31:39 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 10:05:18 +0000
commitd7bf3ad9397a367021e57d204438a178022aaa8c (patch)
tree6adfaa6792bf77ea1369ddccde81d027680b2482 /src/mainboard/intel
parentae4fb10240801ba3e55b83ef2c5cdf99b049d3ea (diff)
downloadcoreboot-d7bf3ad9397a367021e57d204438a178022aaa8c.tar.xz
haswell: Compute disabled channel masks at runtime
All mainboards have a non-zero SPD address to implemented DIMM slots. Knowing this, it is possible to compute the MRC slot population masks automatically instead of hardcoding the values on each mainboard. Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 6bb09a56bc..a156095bef 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -52,14 +52,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
- /*
- * 0 = leave channel enabled
- * 1 = disable dimm 0 on channel
- * 2 = disable dimm 1 on channel
- * 3 = disable dimm 0+1 on channel
- */
- pei_data->dimm_channel0_disabled = 0;
- pei_data->dimm_channel1_disabled = 0;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {