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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 14:57:06 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-26 20:53:23 +0000
commitd8f44360054b6f63d4cf76be179c4d1193e456ae (patch)
tree53231193564a5610413ea674c8962b56b460b8ac /src/mainboard/intel
parenta7d92668326adbe61d29b476cd4676decca131eb (diff)
downloadcoreboot-d8f44360054b6f63d4cf76be179c4d1193e456ae.tar.xz
mb/intel/saddlebrook/devicetree.cb: Use PCH_IRQ* macros
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I6375f97bc2a30beba5882792328f26e0675621cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43867 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 7c2a7d7f35..9243d55b97 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -175,14 +175,14 @@ chip soc/intel/skylake
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0a"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"