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authorAngel Pons <th3fanbus@gmail.com>2020-07-26 17:17:24 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-07 10:12:17 +0000
commitdefdc8539ba11207a7b2a330cc4b6d0474b6f1fb (patch)
tree34434bb454dbda715d01789bb441a08a9f88d1e8 /src/mainboard/intel
parent33aa115574ef70c3ae5baf1a2e489a9a7573052e (diff)
downloadcoreboot-defdc8539ba11207a7b2a330cc4b6d0474b6f1fb.tar.xz
mb/intel/kblrvp: Factor out `HeciEnabled`
RVP8 does not set it, and the other variants set it to zero. So, factor it out. Tested with BUILD_TIMELESS=1, all four variants do not change. Change-Id: I67c958af2dc955d07b895dc93fbe2232dbd48d34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43908 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb1
4 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 0b1ba1d9bc..580f5b0eae 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -23,6 +23,7 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
+ register "HeciEnabled" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 9c9a2e767b..4c2225a8ae 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -9,7 +9,6 @@ chip soc/intel/skylake
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
- register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index 26be7dd751..11f9c01501 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -13,7 +13,6 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0201"
# FSP Configuration
- register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
# VR Settings Configuration for 4 Domains
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 18d764bf13..25dc49ea51 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
- register "HeciEnabled" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"