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| author | Angel Pons <th3fanbus@gmail.com> | 2020-04-15 15:01:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-22 13:46:42 +0000 |
| commit | e8abb5ab8887969498f9953e76b7e0f4c68d3e47 (patch) | |
| tree | caa873b8cb43e06833f2f130c6030aea7f181bf2 /src/mainboard/intel | |
| parent | 52353d09fc981c48b58ebf8bf44f18ad12e119d2 (diff) | |
| download | coreboot-e8abb5ab8887969498f9953e76b7e0f4c68d3e47.tar.xz | |
nb/intel/haswell: Deprecate WDB params in pei_data
The WDB (Write Data Buffer) is a data region in CAR, used as a
scratchpad in the read and write training algorithms of memory
initialization. Both SNB and IVB use this buffer, but HSW does not.
Unlike earlier chipsets, Haswell contains much more in-hardware memory
training machinery, known as REUT (Robust Electrical Unified Testing).
Among other changes, the REUT hardware has a pattern storage buffer,
which renders the need for a pattern storage buffer in CAR obsolete.
Deprecate the WDB-related parameters in the pei_data structure for
Haswell, as they are leftovers from the previous generation's MRC.
Remove them from the mainboards, and explain why they are not required.
Because the MRC ABI has to remain the same, the layout of pei_data must
not be changed, so rename the WDB parameters instead of deleting them.
Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf.
Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b89d13593c..dbe5ed9a4d 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -59,8 +59,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, |