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authorFelix Singer <felixsinger@posteo.net>2020-07-25 14:31:58 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-29 21:04:24 +0000
commit048d9b5cba64d1dbffc40ee19a5263aeac628e3c (patch)
treee3dafeed05f2a9094463616b16d5a555c37ec93d /src/mainboard/intel
parent91dfb920383a8761711e1312f2bcffd2f9529dfb (diff)
downloadcoreboot-048d9b5cba64d1dbffc40ee19a5263aeac628e3c.tar.xz
soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting. Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb2
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb1
5 files changed, 3 insertions, 5 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 0262498623..0b1ba1d9bc 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -157,7 +157,7 @@ chip soc/intel/skylake
device pci 1f.0 on end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
+ device pci 1f.3 off end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index b7b569d7cc..cfb50e3e20 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/skylake
# FSP Configuration
- register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "ScsEmmcHs400Enabled" = "0"
@@ -126,6 +125,7 @@ chip soc/intel/skylake
device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.6 off end # SDCard
+ device pci 1f.3 on end # Intel HDA
device pci 1f.6 on end # GbE
end
end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index a269d01458..5cfb10da50 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0201"
# FSP Configuration
- register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "HeciEnabled" = "0"
@@ -134,5 +133,6 @@ chip soc/intel/skylake
device pnp 0c31.0 on end
end
end # LPC Interface
+ device pci 1f.3 on end # Intel HDA
end
end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 283c0a1f20..aebda8567c 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -24,7 +24,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
- register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index a8066d5cb2..2a0558e190 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -18,7 +18,6 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
# FSP Configuration
- register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "0"