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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 20:18:24 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-14 11:30:34 +0000
commit2452afbe04584d48a9d76535f943c0cfc641aa19 (patch)
tree0ce5aed52511660ab274d8a0aeb95cb606a7b57a /src/mainboard/intel
parentaa990e928910e35edb115095898c4668becdf1d8 (diff)
downloadcoreboot-2452afbe04584d48a9d76535f943c0cfc641aa19.tar.xz
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index c0127b6c45..0d7c162272 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -20,7 +20,6 @@
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/x4x/x4x.h>
-#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/winbond/common/winbond.h>
@@ -31,12 +30,6 @@
static void mb_lpc_setup(void)
{
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
- pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
-
/* Set GPIOs on superio, enable UART */
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_set_logical_device(SERIAL_DEV);
@@ -48,12 +41,6 @@ static void mb_lpc_setup(void)
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
-
- ich7_setup_cir();
}
void mainboard_romstage_entry(void)
@@ -72,6 +59,7 @@ void mainboard_romstage_entry(void)
enable_smbus();
+ i82801gx_early_init();
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();