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authorBora Guvendik <bora.guvendik@intel.com>2017-10-13 15:15:48 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-17 22:49:43 +0000
commit530c6f9cc8dd2c0cd0c586d3d14f11cb8021242f (patch)
treeb89237270f18e4c66b93061f223b03317579e6f9 /src/mainboard/intel
parentde897a6dba1bc6ce157aed8c00cc20642c5d6c59 (diff)
downloadcoreboot-530c6f9cc8dd2c0cd0c586d3d14f11cb8021242f.tar.xz
intel/cannonlake_rvp: enable HS400
Set SCS emmc HS400 enable FSP parameter. TEST=Boot to OS, verify HS400 SDHCI print Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22008 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 00c3e0020e..54d2a69a0f 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -9,6 +9,7 @@ chip soc/intel/cannonlake
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 086d650737..bb75605b11 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -9,6 +9,7 @@ chip soc/intel/cannonlake
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"