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authorArthur Heymans <arthur@aheymans.xyz>2019-04-12 20:10:45 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 09:57:39 +0000
commit7a50554e2965e02045bf314b5d4aa3e3af082c1e (patch)
tree9e47ee3ae12ac4a1cf1aa520489908b257b11a48 /src/mainboard/intel
parent6f5225c7e0ad7a373af1decc212cde5c33b00730 (diff)
downloadcoreboot-7a50554e2965e02045bf314b5d4aa3e3af082c1e.tar.xz
src/mainboard/{foxconn/d41s,intel/d510mo}: Use pci_or_config
The pci_or_configx function makes the code shorter and more readable. Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/d510mo/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index c91d40e890..024c3e10fe 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -28,8 +28,7 @@ void mb_enable_lpc(void)
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
/* Decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
- pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
+ pci_or_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
| CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN
| COMB_LPC_EN);