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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-21 21:51:19 -0800 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-24 09:52:54 +0000 |
| commit | 815d96a975d67db73b8299b3c521b74cf9725b99 (patch) | |
| tree | 45f9b592894340e32c2899401fef0c67e5de0f79 /src/mainboard/intel | |
| parent | 8b3380044d91133c8e5d629a10ef7a3449de8ae3 (diff) | |
| download | coreboot-815d96a975d67db73b8299b3c521b74cf9725b99.tar.xz | |
soc/intel/tigerlake: Enable SATA
Configure SATA FSP UPD according to mainboard design.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions