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authorSubrata Banik <subrata.banik@intel.com>2018-06-04 10:10:31 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-06-05 15:51:40 +0000
commit925ea51e4c9b04b84aa35a44644f4a123bc9a3ee (patch)
tree9fa3cde57dc559123b56bd0de9b780cc94eb01bb /src/mainboard/intel
parentce23d4c6f179358bf84cbdfa678d0435ae3b4cbe (diff)
downloadcoreboot-925ea51e4c9b04b84aa35a44644f4a123bc9a3ee.tar.xz
soc/intel/cannonlake: Add option to skip coreboot MP init
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for CNL. Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 18aa65d890..d5d806c91e 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8bcb850f15..4c62800483 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"