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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2017-09-10 17:37:24 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-14 21:11:02 +0000
commit982688a41ae91218fbb2cfbdb8ff19005ffce0f9 (patch)
tree8c5c811ba15be267087ccc7425183b15ba46b8e1 /src/mainboard/intel
parentb2d6902086d6b7058d8d7a31959c1a16264e4092 (diff)
downloadcoreboot-982688a41ae91218fbb2cfbdb8ff19005ffce0f9.tar.xz
mainboard/intel/cannonlake_rvp-u: Configure USB ports
Configure USB2, USB3 and Type-C ports for CannonLake-U RVP Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index dad18e7ff7..baf951015e 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -10,6 +10,24 @@ chip soc/intel/cannonlake
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device