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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-09 11:59:00 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-14 09:32:34 +0000
commitb0f1988f893bf5f581917816b11e810309955143 (patch)
treec4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/mainboard/intel
parent68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff)
downloadcoreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 43d14ede49..71fed875de 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -62,7 +62,7 @@ chip soc/intel/skylake
# Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
register "SerialIrqConfigSirqEnable" = "0x01"
- register "SerialIrqConfigSirqMode" = "0x01"
+ register "SerialIrqConfigSirqMode" = "0x01"
# VR Settings Configuration for 5 Domains
#+----------------+-------+-------+-------------+-------------+-------+
@@ -226,17 +226,17 @@ chip soc/intel/skylake
[7] = 1, \
}"
register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoPci, \
- [PchSerialIoIndexI2C3] = PchSerialIoPci, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoPci, \
- [PchSerialIoIndexSpi0] = PchSerialIoPci, \
- [PchSerialIoIndexSpi1] = PchSerialIoPci, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoPci, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C3] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi0] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
# PL2 override 25W