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authorShaunak Saha <shaunak.saha@intel.com>2020-03-25 11:42:12 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:37:39 +0000
commitd72cca0c44bc944fdfbdcbc4b264ba0c3727649b (patch)
treef7ed68bc36461ddde13b35e949943b6200a126c7 /src/mainboard/intel
parent1e40a115778865e60a13cb71fdf18eb3ddf1751f (diff)
downloadcoreboot-d72cca0c44bc944fdfbdcbc4b264ba0c3727649b.tar.xz
mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2. BUG=None TEST=build and boot tglrvp Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb8
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb8
2 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 23737c3070..8fd9087c7f 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -4,6 +4,14 @@ chip soc/intel/tigerlake
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index f2e5510147..4ff35cc437 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -4,6 +4,14 @@ chip soc/intel/tigerlake
device lapic 0 on end
end
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"