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authorRonak Kanabar <ronak.kanabar@intel.com>2020-04-06 16:37:01 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-04-13 06:45:10 +0000
commitda968d5f2eb702aecc8374a36faa7dc583e15f7f (patch)
tree2a8913124224a10f5d9c996c3c35e7e379e4fbb1 /src/mainboard/intel
parentd7564dc1b95e0a3a0507ccbc0c7b97e52ec39191 (diff)
downloadcoreboot-da968d5f2eb702aecc8374a36faa7dc583e15f7f.tar.xz
mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP
Enable S0ix from devicetree for JSLRVP TEST= Build, boot JSLRVP and Verified S0ix is working by running "echo freeze > /sys/power/state" from kernel console. Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 76ad831e4c..e8fc451661 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -124,7 +124,7 @@ chip soc/intel/jasperlake
register "dptf_enable" = "1"
# Enable S0ix
- register "s0ix_enable" = "0"
+ register "s0ix_enable" = "1"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,