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authorWenkai Du <wenkai.du@intel.com>2015-08-21 13:11:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-29 07:32:00 +0000
commit1105fad6eaae6e4cfb599cffeaca576084719ce8 (patch)
tree67cf4355ecb1c9703509119ecfe22a15b4ed8a68 /src/mainboard/intel
parenta0f515354be6b852eea9e4dfcb99198523e52579 (diff)
downloadcoreboot-1105fad6eaae6e4cfb599cffeaca576084719ce8.tar.xz
intel/kunimitsu: fix kepler probing
The patch was ported from commit: glados: fix kepler probing BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted kunimitsu. lscpi shows the device on bus 2. Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Originally-signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810 Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11431 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/kunimitsu/gpio.h8
-rw-r--r--src/mainboard/intel/kunimitsu/romstage.c11
2 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 0dbf7826a3..f1166c8539 100644
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -23,6 +23,7 @@
#include <soc/gpio.h>
+/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
@@ -189,4 +190,11 @@ static const struct pad_config gpio_table[] = {
/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* LANPHYC */ /* GPD11 */
};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+};
+
#endif
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index c0d7aec2db..1491794cd9 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -29,11 +29,22 @@
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/romstage.h>
+#include "gpio.h"
#include "spd/spd.h"
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't be. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
void mainboard_romstage_entry(struct romstage_params *params)
{
post_code(0x31);
+ early_config_gpio();
+
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);