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authorArthur Heymans <arthur@aheymans.xyz>2019-01-04 14:23:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-09 09:56:06 +0000
commit4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch)
treee9b31b8b64518a62f6a7885a1de54171471c918b /src/mainboard/intel
parent907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff)
downloadcoreboot-4513020064cc4765e723f6f3cc2b8a45a0dc6545.tar.xz
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/d510mo/romstage.c4
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c5
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c3
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c3
4 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 8d5224e19f..8648e20de0 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -37,7 +37,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)
-
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
@@ -93,9 +92,6 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
int boot_path;
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
if (bist == 0)
enable_lapic();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 9a4e0675b6..5e3535ad2b 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -20,7 +20,6 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-#include <timestamp.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@ -125,10 +124,6 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
if (bist == 0)
enable_lapic();
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 830bc73d75..d1bf1bd1e4 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -82,9 +82,6 @@ void mainboard_romstage_entry(unsigned long bist)
u8 boot_path = 0;
u8 s3_resume;
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_lpc_setup();
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 36aa1498b5..aa8c50ec05 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -75,9 +75,6 @@ void mainboard_romstage_entry(unsigned long bist)
u8 boot_path = 0;
u8 s3_resume;
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
mb_gpio_init();