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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-15 12:36:57 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-05-26 07:16:00 +0200 |
| commit | 56c7dc797246bf4e82879de23436783bbbe54b77 (patch) | |
| tree | fd20140428d918a8e1b43a46c0365f3d2b39810b /src/mainboard/intel | |
| parent | 5649b08e20413f21308951b72c583e926fe2d1f1 (diff) | |
| download | coreboot-56c7dc797246bf4e82879de23436783bbbe54b77.tar.xz | |
Move subsystem IDs to devicetree.cb
A while back coreboot was changed to read the subsystem IDs from
devicetree.cb to allow each onboard PCI device to have its own
subsystem id. When we originally branched, this was not the case,
and the sandybridge/ivybridge mainboards have not been updated yet.
Also, drop the subsystem ID from Emerald Lake 2, since it's not a
Google device.
Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1042
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/Kconfig | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 9e4f34746d..873d273e1f 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -43,12 +43,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - endif # BOARD_INTEL_EMERALDLAKE2 |