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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-10 19:35:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:11:49 +0200 |
| commit | 710566093a504f0fecb641661c5379cad268189b (patch) | |
| tree | 3707b8c91b624e0e4dd40653d46674200eb03dc6 /src/mainboard/intel | |
| parent | 2459f677310efdde229bab3406b2fb5d91f5ec20 (diff) | |
| download | coreboot-710566093a504f0fecb641661c5379cad268189b.tar.xz | |
riscv-spike: Move coreboot to 0x80000000 (2GiB)
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions