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authorPatrick Georgi <patrick@georgi-clan.de>2010-11-15 19:44:42 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-11-15 19:44:42 +0000
commitc2bf26d2477aee7d606a5933017f9f98f4e82303 (patch)
treed3e1e7e89bca6be21277e9651e98291e8daf8d6f /src/mainboard/intel
parenta69d978be8a068944466e776de87527fb104a878 (diff)
downloadcoreboot-c2bf26d2477aee7d606a5933017f9f98f4e82303.tar.xz
Move RCBA defines to northbridge (instead of mainboard)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 8e1d212363..072dad67f8 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -39,6 +39,7 @@
#include "reset.c"
#include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include "northbridge/intel/i3100/i3100.h"
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@@ -54,10 +55,6 @@
#define SATA_MODE_IDE 0x00
#define SATA_MODE_AHCI 0x01
-/* RCBA registers */
-#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
-
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */