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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-06-16 17:24:14 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-18 21:17:27 +0200 |
| commit | c94d73e0e6703369831fe6d489a20d71ab2bb974 (patch) | |
| tree | c02321f3815f217665c57fd159fb43b2a1e47788 /src/mainboard/intel | |
| parent | 401b8accf8fdade02f40f528812ac081c7a0f432 (diff) | |
| download | coreboot-c94d73e0e6703369831fe6d489a20d71ab2bb974.tar.xz | |
mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.
Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/romstage.c | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index ad3a404a14..389a13cd47 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -35,10 +35,6 @@ config MAX_CPUS int default 16 -config SIO_PORT - hex - default 0x164e - config SMBIOS_SYSTEM_ENCLOSURE_TYPE hex default 0x09 # This is a mobile platform diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 69389257d2..add6ddc192 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -44,6 +44,8 @@ #include "gpio.h" #include <arch/stages.h> +#define SIO_PORT 0x164e + static inline void reset_system(void) { hard_reset(); @@ -69,7 +71,7 @@ static void pch_enable_lpc(void) /* Map a range for the runtime registers to the LPC bus. */ pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - if (sio1007_enable_uart_at(CONFIG_SIO_PORT)) { + if (sio1007_enable_uart_at(SIO_PORT)) { pci_write_config16(dev, LPC_EN, lpc_config | COMA_LPC_EN); } @@ -77,7 +79,7 @@ static void pch_enable_lpc(void) static void setup_sio_gpios(void) { - const u16 port = CONFIG_SIO_PORT; + const u16 port = SIO_PORT; const u16 runtime_port = 0x180; /* Turn on configuration mode. */ |