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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:49:12 +0200 |
| commit | 15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch) | |
| tree | 99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/mainboard/intel | |
| parent | 4c3de9c3edd7cb6fabc72337171862930354f0bf (diff) | |
| download | coreboot-15fa992cc8467b4cbd8ebea62e3e4c947827137e.tar.xz | |
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/eagleheights/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 47675a5317..c254f17b7e 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -26,6 +26,7 @@ #include <console/console.h> #include <delay.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <cpu/intel/speedstep.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" @@ -117,8 +118,7 @@ static void early_config(void) pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { /* int boot_mode = 0; */ |