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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:43:48 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:43:20 +0200 |
| commit | 408d3928236f275633f8656cc12e32949d304d9f (patch) | |
| tree | a02149efa1a0b57c0ed8b5afe4bb76f98d35bff2 /src/mainboard/intel | |
| parent | 07921540dda79d810d8bfc6be211513c238a0d63 (diff) | |
| download | coreboot-408d3928236f275633f8656cc12e32949d304d9f.tar.xz | |
intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/d510mo/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 28481c026f..f73bf649a9 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -24,6 +24,7 @@ #include <northbridge/intel/pineview/raminit.h> #include <northbridge/intel/pineview/pineview.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/lapic.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <superio/winbond/common/winbond.h> @@ -33,7 +34,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -#include <cpu/intel/romstage.h> /* Early mainboard specific GPIO setup */ static void mb_gpio_init(void) @@ -102,7 +102,7 @@ static void rcba_config(void) RCBA32(0x3418) |= 1; } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f46cdc03c6..8077ba212d 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -149,8 +150,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; |