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| author | Nico Huber <nico.huber@secunet.com> | 2017-06-28 16:42:51 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-06-29 15:41:02 +0000 |
| commit | 5f9c6734fc9bbe69c007c46c8ec6f314bd5522a8 (patch) | |
| tree | 8f8ae84291f503c88a92103e5c528b7b0d284b46 /src/mainboard/intel | |
| parent | 956cfa307b59ff035f47a6bf4b21456963991839 (diff) | |
| download | coreboot-5f9c6734fc9bbe69c007c46c8ec6f314bd5522a8.tar.xz | |
lib/spd_bin: Use proper I2C addresses
Use the plain address instead of the weird shifted encoding (e.g. if
we'd use `0xa0` as address, it's actually `0x50` encoded into a write
command).
Change-Id: I6febb2e04e1c6de4294dfa37bde16b147a80b7a8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/kblrvp/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 9082254385..7bfbe1c744 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -51,7 +51,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ struct spd_block blk = { - .addr_map = { 0xa0, 0xa2, 0xa4, 0xa6, }, + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, }; mem_cfg->DqPinsInterleaved = 1; |