diff options
| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2017-12-12 23:08:42 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-01-07 02:00:15 +0000 |
| commit | b5b53db8fece34913731eeda9bcb2b87a09c76cb (patch) | |
| tree | 14cfcc3a9a126af8d86b9fb7fbec66c4792ff8bb /src/mainboard/intel | |
| parent | 4f512dba5f02ae306277ac50b6ef0c13c45d012b (diff) | |
| download | coreboot-b5b53db8fece34913731eeda9bcb2b87a09c76cb.tar.xz | |
intel/dcp847ske: Add superio ACPI declarations
Tested on Linux 4.13.14:
SuperIO resources show up as reserved in /proc/ioports and friends.
Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/acpi/superio.asl | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 09f905ee8f..aefb51d25e 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -1 +1,28 @@ -/* Dummy file required by pch.asl - No license necessary. */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x4e + +#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#define NCT6776_SHOW_SP1 1 +#endif +#define NCT6776_SHOW_HWM 1 +#define NCT6776_SHOW_GPIO 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" |