Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board

which uses it.

Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 642 insertions, 0 deletions

diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl b/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl
new file mode 100644
index 0000000000..6f8d3127a2
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/cpu.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Core (2) Duo CPU node support
+ *
+ * Note: The ACPI P_BLK on the ICH7 (and probably others) lives at
+ * PMBASE + 0x10, and it's 0x06 bytes long. On ICH8 it's 8 bytes.
+ *
+ * The second CPU core does not need its own P_BLK.
+ */
+
+Scope(\_PR)
+{
+	Processor(
+		CPU1,	// name of cpu/core 0
+		1,	// numeric id of cpu/core
+		0x510,	// ACPI P_BLK base address
+		6	// ACPI P_BLK size
+	)
+	{
+		// TODO: _PDT
+	}
+
+	Processor(
+		CPU2,	// name of cpu/core 1
+		2,	// numeric id of cpu/core 1
+		0,	// ACPI P_BLK base address
+		0)	// ACPI P_BLK size
+	{
+		// TODO: _PDT
+	}
+}	// End _PR
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl
new file mode 100644
index 0000000000..680f6cb2be
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000
+		// for EC initialization before a driver
+		// is loaded
+	}
+
+	Name (_GPE, 23)	// GPI07 / GPE23 -> Runtime SCI
+
+	// TODO EC Query methods
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/globalnvs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/globalnvs.asl
new file mode 100644
index 0000000000..70c2dac0dc
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/globalnvs.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name(\PICM,0)			// IOAPIC/8259
+
+/* Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xFF)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x00),
+	OSYS,	16,	// 0x00 Operating System
+	SMIF,	 8,	// 0x02 SMI function
+	Offset (0x10),
+	MPEN,	 8,	// 0x10 Multi Processor Enable
+
+}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl
new file mode 100644
index 0000000000..e466658dd4
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/northbridge_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			Package() { 0x0001ffff, 1, 0, 17 },
+			Package() { 0x0001ffff, 2, 0, 18 },
+			Package() { 0x0001ffff, 3, 0, 19 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 23 },
+			Package() { 0x001dffff, 1, 0, 19 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 16 },
+			// AC97/IDE				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, 0, 17 },
+			Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 18 },
+			Package() { 0x001fffff, 1, 0, 19},
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// AC97/IDE			0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl b/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl
new file mode 100644
index 0000000000..fe2ba93394
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/platform.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	//Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Call a trap so SMI can prepare for Sleep as well.
+	// TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl b/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl
new file mode 100644
index 0000000000..61595854b2
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/sleepstates.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\_S0, Package(4){0x0,0x0,0,0})
+Name(\_S1, Package(4){0x1,0x0,0,0})
+Name(\_S3, Package(4){0x5,0x0,0,0})
+Name(\_S4, Package(4){0x6,0x0,0,0})
+Name(\_S5, Package(4){0x7,0x0,0,0})
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl b/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl
new file mode 100644
index 0000000000..c108d3f5b2
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/southbridge_pci_irqs.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, 0, 16},
+
+		Package() { 0x0001ffff, 0, 0, 20},
+		Package() { 0x0001ffff, 1, 0, 21},
+		Package() { 0x0001ffff, 2, 0, 22},
+		Package() { 0x0001ffff, 3, 0, 23},
+
+		Package() { 0x0002ffff, 0, 0, 21},
+		Package() { 0x0002ffff, 1, 0, 22},
+		Package() { 0x0002ffff, 2, 0, 23},
+		Package() { 0x0002ffff, 3, 0, 20},
+
+		Package() { 0x0003ffff, 0, 0, 22},
+		Package() { 0x0003ffff, 1, 0, 23},
+		Package() { 0x0003ffff, 2, 0, 20},
+		Package() { 0x0003ffff, 3, 0, 21},
+
+		Package() { 0x0004ffff, 0, 0, 23},
+		Package() { 0x0004ffff, 1, 0, 20},
+		Package() { 0x0004ffff, 2, 0, 21},
+		Package() { 0x0004ffff, 3, 0, 22},
+
+		Package() { 0x0005ffff, 0, 0, 19},
+		Package() { 0x0005ffff, 1, 0, 18},
+		Package() { 0x0005ffff, 2, 0, 17},
+		Package() { 0x0005ffff, 3, 0, 16},
+
+		Package() { 0x0006ffff, 0, 0, 18},
+		Package() { 0x0006ffff, 1, 0, 17},
+		Package() { 0x0006ffff, 2, 0, 16},
+		Package() { 0x0006ffff, 3, 0, 19},
+
+		Package() { 0x0009ffff, 0, 0, 21},
+		Package() { 0x0009ffff, 1, 0, 22},
+		Package() { 0x0009ffff, 2, 0, 23},
+		Package() { 0x0009ffff, 3, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl b/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl
new file mode 100644
index 0000000000..d2498d4e5b
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/superio.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+	Name (_HID, EISAID("PNP0A05"))
+	Name (_UID, 1)
+
+	Device (UAR1)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+
+	Device (UAR2)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 2)
+
+		// Some methods need an implementation here:
+		// missing: _STA, _DIS, _CRS, _PRS,
+		// missing: _SRS, _PS0, _PS3
+	}
+}
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl
new file mode 100644
index 0000000000..b7a6e82342
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/thermal.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+
+		// FIXME these could/should be read from the
+		// GNVS area, so they can be controlled by
+		// coreboot
+		Name(TC1V, 0x04)
+		Name(TC2V, 0x03)
+		Name(TSPV, 0x64)
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (0xf5c) // Value for Rocky
+		}
+
+		// Method (_AC1, 0, Serialized)
+		// {
+		// 	Return (0xf5c)
+		// }
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Return (Add (0x0aac, 0x50)) // FIXME
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Return (0xaaf) // FIXME
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			Return (0xaac) // FIXME
+		}
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU1, \_PR.CPU2})
+			}
+			Return (Package() {\_PR.CPU1})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+
+
+	}
+}
+
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl b/src/mainboard/iwave/iWRainbowG6/acpi/video.asl
new file mode 100644
index 0000000000..507a390d27
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/acpi/video.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+