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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-03 15:53:33 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-17 21:38:17 +0200 |
| commit | 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e (patch) | |
| tree | 2c7dda58587f464fa1baee712c95bb48c924ff76 /src/mainboard/iwave/iWRainbowG6/dsdt.asl | |
| parent | 083da160af4a0e3a76506af59477f105d78b9683 (diff) | |
| download | coreboot-4bab6e79b078c76d0a42883c4b4c9c68615d5a1e.tar.xz | |
intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/iwave/iWRainbowG6/dsdt.asl')
| -rw-r--r-- | src/mainboard/iwave/iWRainbowG6/dsdt.asl | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl index a33744577a..0dc46f2caa 100644 --- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl +++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", 0x02, // DSDT revision: ACPI v2.0 - "COREv2", // OEM id + "COREv4", // OEM id "COREBOOT", // OEM table id 0x20090419 // OEM revision ) @@ -26,7 +26,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include <southbridge/intel/sch/acpi/globalnvs.asl> + #include <soc/intel/sch/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -36,11 +36,10 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/sch/acpi/sch.asl> - #include <southbridge/intel/sch/acpi/sch.asl> + #include <soc/intel/sch/acpi/sch.asl> } } /* Chipset specific sleep states */ - #include <southbridge/intel/sch/acpi/sleepstates.asl> + #include <soc/intel/sch/acpi/sleepstates.asl> } |