summaryrefslogtreecommitdiff
path: root/src/mainboard/iwave
diff options
context:
space:
mode:
authorJonathan A. Kollasch <jakllsch@kollasch.net>2015-07-07 12:57:46 -0500
committerJonathan A. Kollasch <jakllsch@kollasch.net>2015-07-14 13:40:07 +0200
commitec505ad21c923c114a16b2710a0113f657765430 (patch)
treec3ecdb6021982e2d79220b63d40448bebe43baf2 /src/mainboard/iwave
parentfb4233bb22602c3802da39200b85845407e0c496 (diff)
downloadcoreboot-ec505ad21c923c114a16b2710a0113f657765430.tar.xz
azalia: fix up and clean up shrinkage of boilerplate code
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/iwave')
-rw-r--r--src/mainboard/iwave/iWRainbowG6/hda_verb.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/hda_verb.c b/src/mainboard/iwave/iWRainbowG6/hda_verb.c
index effc22ea8d..21b230b8ca 100644
--- a/src/mainboard/iwave/iWRainbowG6/hda_verb.c
+++ b/src/mainboard/iwave/iWRainbowG6/hda_verb.c
@@ -17,7 +17,9 @@
* Foundation, Inc.
*/
-static u32 mainboard_cim_verb_data[] = {
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
/* coreboot specific header */
0x111d76d5, // Codec Vendor / Device ID: IDT 92HD81
0x00000000, // Subsystem ID
@@ -89,4 +91,7 @@ static u32 mainboard_cim_verb_data[] = {
/* BTL Gain */
0x017F417, /* Gain = 16.79dB */
};
+
+const u32 pc_beep_verbs[0] = {};
+
AZALIA_ARRAY_SIZES;