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| author | Patrick Georgi <patrick.georgi@secunet.com> | 2012-11-20 11:53:47 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-27 23:51:52 +0100 |
| commit | e135ac5a7ea69b6edcb89345019212f5de412b1e (patch) | |
| tree | 408611a9f2846867f9731af53b1f08dd32eb6851 /src/mainboard/iwill/dk8_htx | |
| parent | bdc1816b2379bdf569ac6746172bba41e1307917 (diff) | |
| download | coreboot-e135ac5a7ea69b6edcb89345019212f5de412b1e.tar.xz | |
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic
LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages
Future work:
- remove the compile time special case
(requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/iwill/dk8_htx')
| -rw-r--r-- | src/mainboard/iwill/dk8_htx/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 906105e8ad..31468176b0 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -14,7 +14,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "cpu/x86/bist.h" #include "lib/delay.c" |