diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/iwill/dk8s2 | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwill/dk8s2')
| -rw-r--r-- | src/mainboard/iwill/dk8s2/irq_tables.c | 2 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8s2/romstage.c | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c index 75f1790abd..c3928f06ff 100644 --- a/src/mainboard/iwill/dk8s2/irq_tables.c +++ b/src/mainboard/iwill/dk8s2/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 8dc9dc0049..9a2fede061 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -165,21 +165,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif |