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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 22:47:22 +0000
commit7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32 (patch)
tree5339d014fbd29d3eb27cc82987eb7d655d9d8d1a /src/mainboard/iwill
parent57b2ff886e0ce2c92820f5722c8031def3ac94cf (diff)
downloadcoreboot-7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32.tar.xz
Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwill')
-rw-r--r--src/mainboard/iwill/dk8_htx/romstage.c47
-rw-r--r--src/mainboard/iwill/dk8s2/romstage.c36
-rw-r--r--src/mainboard/iwill/dk8x/romstage.c46
3 files changed, 43 insertions, 86 deletions
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index fdc7199c70..75584f3090 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -50,14 +50,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -81,34 +79,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // second node
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +135,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 45d2e6c10d..70339e82be 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -49,15 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -92,23 +90,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 45d2e6c10d..b8169b2b94 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -49,15 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -81,34 +79,29 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif