diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-14 11:40:34 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-14 11:40:34 +0000 |
| commit | 5d3dee8334c2303434d7b00bec3aad4911120ac1 (patch) | |
| tree | 38fd30e2473dc76d9cd64092133127934f184e9e /src/mainboard/iwill | |
| parent | 4154c668f24da79672099dfac06f5263c415fee0 (diff) | |
| download | coreboot-5d3dee8334c2303434d7b00bec3aad4911120ac1.tar.xz | |
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iwill')
| -rw-r--r-- | src/mainboard/iwill/dk8_htx/romstage.c | 15 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8s2/romstage.c | 15 | ||||
| -rw-r--r-- | src/mainboard/iwill/dk8x/romstage.c | 15 |
3 files changed, 21 insertions, 24 deletions
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 580a76b64b..c34b2830f4 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 01244a0559..8f9e4f488a 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 01244a0559..8f9e4f488a 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { |