Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this

changes the superio to a Fintek F71805F as described at
http://www.coreboot.org/Jetway_J7F2_Build_Tutorial

It also creates the mainboard tree for this series of motherboards
(Jetway J7F2 and J7F4).  I've tested it with one motherboard
(J7F2WE1G3), and I believe it works with the others, as the differences
among them are mostly trivial (processor speed, chipset and quantity of
LAN cards, audio chipset, etc.).  A list of the relevant motherboards
with specs can be found at
http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16

The irq_tables.c is copied directly from the epia-cn, because the one
generated by getpir with the factory BIOS did not work properly while
the EPIA-CN one did.

Minor changes on checkin to cope with moved romcc in latest revision.

NOTE: This board is broken until the issue introduced in r3567 is resolved.

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 108 insertions, 0 deletions

diff --git a/src/mainboard/jetway/j7f24/Options.lb b/src/mainboard/jetway/j7f24/Options.lb
new file mode 100644
index 0000000000..7d392c4b84
--- /dev/null
+++ b/src/mainboard/jetway/j7f24/Options.lb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_PAYLOAD
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses COREBOOT_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses HAVE_ACPI_TABLES
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES
+uses TTYS0_BAUD
+uses CONFIG_CHIP_NAME
+uses CONFIG_VIDEO_MB
+uses CONFIG_IOAPIC
+
+default ROM_SIZE = 512 * 1024
+default CONFIG_IOAPIC = 0
+default CONFIG_VIDEO_MB = 32
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_PCI_ROM_RUN = 0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_CHIP_NAME = 1
+default HAVE_FALLBACK_BOOT = 1
+default HAVE_MP_TABLE = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+default HAVE_HARD_RESET = 0
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 10
+default HAVE_ACPI_TABLES = 0
+default HAVE_OPTION_TABLE = 1
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = ROM_SIZE
+default USE_FALLBACK_IMAGE = 1
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 16 * 1024
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+default _RAMBASE = 0x00004000
+default CONFIG_ROM_PAYLOAD = 1
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
+default HOSTCC = "gcc"
+
+##
+## Set this to the max PCI bus number you would ever use for PCI config I/O.
+## Setting this number very high will make pci_locate_device() take a long
+## time when it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 3
+
+end
+