summaryrefslogtreecommitdiff
path: root/src/mainboard/jetway/j7f2
diff options
context:
space:
mode:
authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-23 21:52:25 +1000
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-26 18:22:11 +0200
commitcf7b4989083cb3fd1adf34dc5e07d4ac253e8f85 (patch)
tree47aba25be42b14b74d97bb68e9e1a4df3f986ca0 /src/mainboard/jetway/j7f2
parent4566d2e7cd32c1c2bdcc85a09c580e9f00f6b1dd (diff)
downloadcoreboot-cf7b4989083cb3fd1adf34dc5e07d4ac253e8f85.tar.xz
superio/fintek/*: Factor out generic romstage component
The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/jetway/j7f2')
-rw-r--r--src/mainboard/jetway/j7f2/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index 37c3ab4186..845561026d 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -31,6 +31,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/early_smbus.c"
+#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71805f/f71805f.h>
#include <lib.h>
#include <spd.h>
@@ -90,7 +91,7 @@ void main(unsigned long bist)
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();