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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:48:32 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-25 20:33:26 +0000 |
| commit | f61ffcf9a489fa5d971f8584450be0869e6ca78d (patch) | |
| tree | 46b0c7ccf0d07fa0511e87e450d0364fc1ff59e6 /src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | |
| parent | 949491979ccec4242fb4398fa954c0678c72cda2 (diff) | |
| download | coreboot-f61ffcf9a489fa5d971f8584450be0869e6ca78d.tar.xz | |
jetway/nf81-t56n-lf: Switch away from AGESA_LEGACY
Change-Id: I6ad0c4cf2f0398f0b1efac1282822acf0d4a3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index f980a15b08..cccb78c4db 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -17,7 +17,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -35,7 +35,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; void *BrazosPcieComplexListPtr; @@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /** @@ -188,12 +187,13 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings. */ -const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} |