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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 21:42:46 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-23 03:35:58 +0000
commit390ba044dcd650e37340f1ddee98bedf1096e76d (patch)
tree9836ee3819e8de8f0b5d67150fb19644e118cefe /src/mainboard/jetway/nf81-t56n-lf
parent14382453349f0ca1c11870ed10f8e7fd839851cc (diff)
downloadcoreboot-390ba044dcd650e37340f1ddee98bedf1096e76d.tar.xz
AGESA binaryPI: Consolidate and fix sleep states
SSFG was meant to be used as a mask to enable sleep states _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. State _S3 is now set conditionally if HAVE_ACPI_RESUME=y. For pi/hudson this had been fixed already preprocessor. Note that all boards had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. States _S1 and _S2 still appear enabled in ASL/AML but may not actually work. TEST: 'cat /sys/power/state' and notice choice 'mem' was removed from the list of available sleep states. Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/dsdt.asl2
2 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
index b666a4f350..702cb92032 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
-Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
index 7e26bab43c..b5d60d4a92 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
@@ -47,7 +47,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"