mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes

Port to recent reference board (AMD Persimmon) changes in commits:

c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing

Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5882
Tested-by: build bot (Jenkins)
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>

3 files changed, 177 insertions, 77 deletions

diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index 8fb079537c..688f9dd929 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -19,6 +19,7 @@
 
 #include "agesawrapper.h"
 
+#include <arch/ioapic.h>
 #include <console/console.h>
 #include <cpu/amd/amdfam14.h>
 #include <device/pci.h>
@@ -37,6 +38,7 @@
 u8 bus_isa;
 u8 bus_sb800[6];
 u32 apicid_sb800;
+u32 apicver_sb800;
 
 /**
  * Here you only need to set value in pci1234 for HT-IO that could be
@@ -145,7 +147,14 @@ void get_bus_conf(void)
 	/* I/O APICs:    APIC ID Version State   Address */
 	bus_isa = 10;
 	apicid_base = CONFIG_MAX_CPUS;
-	apicid_sb800 = apicid_base;
+
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
 
 #if CONFIG_AMD_SB_CIMX
 	sb_Late_Post();
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index 7e1c367ae7..7ad30028f6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,11 +31,107 @@
 #include <device/pci_def.h>
 
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/sb800/sb800.h>
+#include <southbridge/amd/cimx/sb800/pci_devs.h>
+#include <southbridge/amd/cimx/cimx_util.h>
+#include <northbridge/amd/agesa/family14/pci_devs.h>
 
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system.  It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair.  These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables.  TODO: Make ACPI use these values too.
+ *
+ * The Persimmon PCI INTA/B/C/D pins are connected to
+ * FCH pins INTE/F/G/H on the schematic so these need
+ * to be routed as well.
+ */
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
+	/* Misc-nil,0,1,2, INT from Serial irq */
+	[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
+	[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
+	/* IMC INT0 - 5 */
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	/* USB Devs 18/19/20/22 INTA-C */
+	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
+	/* IDE, SATA */
+	[0x40] = 0x0B,0x0B,
+	/* GPPInt0 - 3 */
+	[0x50] = 0x0A,0x0B,0x0A,0x0B
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+	/* Misc-nil,0,1,2, INT from Serial irq */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
+	/* IMC INT0 - 5 */
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	/* USB Devs 18/19/22/20 INTA-C */
+	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
+	/* IDE, SATA */
+	[0x40] = 0x11,0x13,
+	/* GPPInt0 - 3 */
+	[0x50] = 0x10,0x11,0x12,0x13
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device.  Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01.  This index will define
+ * the interrupt that it should use.  Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+/*
+ * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
+ * but because PCI INT_PIN swizzling isnt implemented to match
+ * the IDSEL (dev 3) of the slot, the table is adjusted for the
+ * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
+ * off-chip devices should get mapped to PIRQH/E/F/G.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+	/* {PCI_devfn,	{PIN A, PIN B, PIN C, PIN D}}, */
+	{GFX_DEVFN,		{PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},	/* VGA:		01.0 */
+	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* NIC:		04.0 */
+	{NB_PCIE_PORT3_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* PCIe bdg:06.0 */
+	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SATA:	11.0 */
+	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI1:	12.0 */
+	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},	/* EHCI1:	12.2 */
+	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI2:	13.0 */
+	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},	/* EHCI2:	13.2 */
+	{SMBUS_DEVFN,	{PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SMBUS:	14.0 */
+	{IDE_DEVFN,	{PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},		/* IDE:		14.1 */
+	{HDA_DEVFN,	{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* HDA:		14.2 */
+	{SB_PCI_PORT_DEVFN,	{PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},	/* PCI bdg:	14.4 */
+	{OHCI4_DEVFN,	{PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}},	/* OHCI4:	14.5 */
+	{OHCI3_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI3:	16.0 */
+	{EHCI3_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},	/* EHCI3:	16.2 */
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	pirq_data_ptr = mainboard_pirq_data;
+	pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
 /**
  * TODO
  * SB CIMx callback
@@ -83,6 +181,9 @@ static void mainboard_enable(device_t dev)
 	 */
 	pm_iowrite(0x29, 0x80);
 	pm_iowrite(0x28, 0x61);
+
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 9be4854348..a97810cf54 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,133 +21,121 @@
 
 
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <console/console.h>
 #include <cpu/amd/amdfam14.h>
 #include <device/pci.h>
+#include <drivers/generic/ioapic/chip.h>
 #include <stdint.h>
 #include <string.h>
 
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+#include <southbridge/amd/cimx/cimx_util.h>
 
 extern u8 bus_sb800[6];
-
 extern u32 apicid_sb800;
+extern u32 apicver_sb800;
 
 extern u32 bus_type[256];
 extern u32 sbdn_sb800;
 
-u8 intr_data[] = {
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x10,0x11,0x12,0x13
-};
-
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
 
+	/* Intialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
-	memcpy(mc->mpc_oem, "JETWAY	 ", 8);
 
+	/*
+	 * Type 0: Processor Entries:
+	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+	 * CPU Signature (Stepping, Model, Family),
+	 * Feature Flags
+	 */
 	smp_write_processors(mc);
 
+	/* Get Bus Configuration */
 	get_bus_conf();
 
+	/*
+	 * Type 1: Bus Entries:
+	 * Bus ID, Bus Type
+	 */
 	mptable_write_buses(mc, NULL, &bus_isa);
 
-	/* I/O APICs:	 APIC ID Version State	 Address */
-
-	u32 dword;
-	u8 byte;
-
-	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-	dword &= 0xFFFFFFF0;
-	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-	outb(byte | 0x80, 0xC00);
-	outb(intr_data[byte], 0xC01);
-	}
-
-	/* I/O Ints:	Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	/*
+	 * Type 2: I/O APICs:
+	 * APIC ID, Version, APIC Flags:EN, Address
+	 */
+	smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
 
+	/*
+	 * Type 3: I/O Interrupt Table Entries:
+	 * Int Type, Int Polarity, Int Level, Source Bus ID,
+	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
+	 */
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
 
-	/* APU Internal Graphic Device*/
-	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device */
+	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
+
+	/* SMBUS / ACPI */
+	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
+
+	/* Southbridge HD Audio */
+	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
 
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-	/* Southbridge HD Audio: */
-	PCI_INT(0x0, 0x14, 0x2, 0x12);
+	/* LPC */
+	PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
 
-	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+	/* USB */
+	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+	PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+	PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
+	PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
+
+	 /* IDE */
+	PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
 
 	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
 
 	/* On-board NIC & Slot PCIE. */
+	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
+	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
 
 	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-	/* On-board Realtek NIC 1. */
-	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	/* PCI_SLOT 0 */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
+	PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
+	PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
+	PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
 
 	/* On-board Realtek NIC 2. (PCIe PortA) */
-	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
 	/* PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
 	/* PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
 	/* PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, 0x13);
+	PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
+
+	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+		smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-	/* Local Ints:
-	 * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN#
-	 */
 	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
@@ -157,6 +147,6 @@ static void *smp_write_config_table(void *v)
 unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
-	v = smp_write_floating_table(addr, 0);
+	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
 	return (unsigned long)smp_write_config_table(v);
 }