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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-23 02:50:00 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:49:18 +0000 |
| commit | b0ae42b5bb7fe7c9f6e8301bff8fbabe95294c62 (patch) | |
| tree | 30c8ecd9f58b4fdaa25f7375a408457415b2554a /src/mainboard/jetway/nf81-t56n-lf | |
| parent | 19edbf640bad4a8f5337c14814a8f7014d83e094 (diff) | |
| download | coreboot-b0ae42b5bb7fe7c9f6e8301bff8fbabe95294c62.tar.xz | |
AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
Use the pre-defined constant address directly.
Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/jetway/nf81-t56n-lf')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 6e0f1ad969..2129509d55 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -43,20 +43,12 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi PCIe_SLOT_RESET_INFO *ResetInfo; uint32_t GpioMmioAddr; - uint32_t AcpiMmioAddr; uint8_t Data8; - uint16_t Data16; FcnData = Data; ResetInfo = ConfigPtr; - /* Get SB800 MMIO Base (AcpiMmioAddr) */ - Data8 = pm_io_read8(0x27); - Data16 = Data8 << 8; - Data8 = pm_io_read8(0x26); - Data16 |= Data8; - AcpiMmioAddr = (uint32_t)Data16 << 16; Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + GpioMmioAddr = ACPIMMIO_GPIO_BASE_100; switch (ResetInfo->ResetId) { case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */ |