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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-21 14:44:13 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-11 11:58:02 +0000 |
| commit | 6d1fdb34105a6ed894ce0aba85b9fb2eb3cf9d33 (patch) | |
| tree | cec8664e1a377809578ef6cc9eb5369b08454c44 /src/mainboard/jetway | |
| parent | f6bbc603fadf4fdb6c9c86775739ff1b32ab5f1e (diff) | |
| download | coreboot-6d1fdb34105a6ed894ce0aba85b9fb2eb3cf9d33.tar.xz | |
AMD fam10: Link southbridge/amd/rs780/early_setup.c
Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/romstage.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 163b2ebe9d..760fc13aed 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -47,7 +47,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> -#include "southbridge/amd/rs780/early_setup.c" +#include <southbridge/amd/rs780/rs780.h> #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); |