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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-24 18:18:20 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-24 18:18:20 +0000
commitb015d02a857b27a65a3ef52839361236645754d2 (patch)
tree25f3b2b53a2d9dc4e91b1fd2004ed9454d325344 /src/mainboard/jetway
parent8a6163e02b7fcbbeb0d3e88569a5df8bc3c7b072 (diff)
downloadcoreboot-b015d02a857b27a65a3ef52839361236645754d2.tar.xz
Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 122c12a23c..24302fe19a 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -67,6 +67,11 @@ static int smbus_read_byte(u32 device, u32 address);
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -146,6 +151,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
+
+#if CONFIG_USBDEBUG
+ sb700_enable_usbdebug(0);
+ early_usbdebug_init();
+#endif
+
console_init();
printk(BIOS_DEBUG, "\n");